1# SPDX-License-Identifier: GPL-2.0-only 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/iommu/arm,smmu.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM System MMU Architecture Implementation 8 9maintainers: 10 - Will Deacon <will@kernel.org> 11 - Robin Murphy <Robin.Murphy@arm.com> 12 13description: |+ 14 ARM SoCs may contain an implementation of the ARM System Memory 15 Management Unit Architecture, which can be used to provide 1 or 2 stages 16 of address translation to bus masters external to the CPU. 17 18 The SMMU may also raise interrupts in response to various fault 19 conditions. 20 21properties: 22 $nodename: 23 pattern: "^iommu@[0-9a-f]*" 24 compatible: 25 oneOf: 26 - description: Qcom SoCs implementing "arm,smmu-v2" 27 items: 28 - enum: 29 - qcom,msm8996-smmu-v2 30 - qcom,msm8998-smmu-v2 31 - qcom,sdm630-smmu-v2 32 - const: qcom,smmu-v2 33 34 - description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500" 35 items: 36 - enum: 37 - qcom,qcm2290-smmu-500 38 - qcom,qdu1000-smmu-500 39 - qcom,sa8775p-smmu-500 40 - qcom,sc7180-smmu-500 41 - qcom,sc7280-smmu-500 42 - qcom,sc8180x-smmu-500 43 - qcom,sc8280xp-smmu-500 44 - qcom,sdm670-smmu-500 45 - qcom,sdm845-smmu-500 46 - qcom,sdx55-smmu-500 47 - qcom,sdx65-smmu-500 48 - qcom,sm6115-smmu-500 49 - qcom,sm6125-smmu-500 50 - qcom,sm6350-smmu-500 51 - qcom,sm6375-smmu-500 52 - qcom,sm8150-smmu-500 53 - qcom,sm8250-smmu-500 54 - qcom,sm8350-smmu-500 55 - qcom,sm8450-smmu-500 56 - qcom,sm8550-smmu-500 57 - const: qcom,smmu-500 58 - const: arm,mmu-500 59 60 - description: Qcom SoCs implementing "arm,mmu-500" (legacy binding) 61 deprecated: true 62 items: 63 # Do not add additional SoC to this list. Instead use two previous lists. 64 - enum: 65 - qcom,qcm2290-smmu-500 66 - qcom,sc7180-smmu-500 67 - qcom,sc7280-smmu-500 68 - qcom,sc8180x-smmu-500 69 - qcom,sc8280xp-smmu-500 70 - qcom,sdm845-smmu-500 71 - qcom,sm6115-smmu-500 72 - qcom,sm6350-smmu-500 73 - qcom,sm6375-smmu-500 74 - qcom,sm8150-smmu-500 75 - qcom,sm8250-smmu-500 76 - qcom,sm8350-smmu-500 77 - qcom,sm8450-smmu-500 78 - const: arm,mmu-500 79 - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500" 80 items: 81 - enum: 82 - qcom,sc7280-smmu-500 83 - qcom,sm6115-smmu-500 84 - qcom,sm6125-smmu-500 85 - qcom,sm8150-smmu-500 86 - qcom,sm8250-smmu-500 87 - qcom,sm8350-smmu-500 88 - const: qcom,adreno-smmu 89 - const: qcom,smmu-500 90 - const: arm,mmu-500 91 - description: Qcom Adreno GPUs implementing "arm,mmu-500" (legacy binding) 92 deprecated: true 93 items: 94 # Do not add additional SoC to this list. Instead use previous list. 95 - enum: 96 - qcom,sc7280-smmu-500 97 - qcom,sm8150-smmu-500 98 - qcom,sm8250-smmu-500 99 - const: qcom,adreno-smmu 100 - const: arm,mmu-500 101 - description: Qcom Adreno GPUs implementing "arm,smmu-v2" 102 items: 103 - enum: 104 - qcom,msm8996-smmu-v2 105 - qcom,sc7180-smmu-v2 106 - qcom,sdm630-smmu-v2 107 - qcom,sdm845-smmu-v2 108 - qcom,sm6350-smmu-v2 109 - const: qcom,adreno-smmu 110 - const: qcom,smmu-v2 111 - description: Qcom Adreno GPUs on Google Cheza platform 112 items: 113 - const: qcom,sdm845-smmu-v2 114 - const: qcom,smmu-v2 115 - description: Marvell SoCs implementing "arm,mmu-500" 116 items: 117 - const: marvell,ap806-smmu-500 118 - const: arm,mmu-500 119 - description: NVIDIA SoCs that require memory controller interaction 120 and may program multiple ARM MMU-500s identically with the memory 121 controller interleaving translations between multiple instances 122 for improved performance. 123 items: 124 - enum: 125 - nvidia,tegra186-smmu 126 - nvidia,tegra194-smmu 127 - nvidia,tegra234-smmu 128 - const: nvidia,smmu-500 129 - items: 130 - const: arm,mmu-500 131 - const: arm,smmu-v2 132 - items: 133 - enum: 134 - arm,mmu-400 135 - arm,mmu-401 136 - const: arm,smmu-v1 137 - enum: 138 - arm,smmu-v1 139 - arm,smmu-v2 140 - arm,mmu-400 141 - arm,mmu-401 142 - arm,mmu-500 143 - cavium,smmu-v2 144 145 reg: 146 minItems: 1 147 maxItems: 2 148 149 '#global-interrupts': 150 description: The number of global interrupts exposed by the device. 151 $ref: /schemas/types.yaml#/definitions/uint32 152 minimum: 0 153 maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters 154 155 '#iommu-cells': 156 enum: [ 1, 2 ] 157 description: | 158 See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a 159 value of 1, each IOMMU specifier represents a distinct stream ID emitted 160 by that device into the relevant SMMU. 161 162 SMMUs with stream matching support and complex masters may use a value of 163 2, where the second cell of the IOMMU specifier represents an SMR mask to 164 combine with the ID in the first cell. Care must be taken to ensure the 165 set of matched IDs does not result in conflicts. 166 167 interrupts: 168 minItems: 1 169 maxItems: 388 # 260 plus 128 contexts 170 description: | 171 Interrupt list, with the first #global-interrupts entries corresponding to 172 the global interrupts and any following entries corresponding to context 173 interrupts, specified in order of their indexing by the SMMU. 174 175 For SMMUv2 implementations, there must be exactly one interrupt per 176 context bank. In the case of a single, combined interrupt, it must be 177 listed multiple times. 178 179 dma-coherent: 180 description: | 181 Present if page table walks made by the SMMU are cache coherent with the 182 CPU. 183 184 NOTE: this only applies to the SMMU itself, not masters connected 185 upstream of the SMMU. 186 187 calxeda,smmu-secure-config-access: 188 type: boolean 189 description: 190 Enable proper handling of buggy implementations that always use secure 191 access to SMMU configuration registers. In this case non-secure aliases of 192 secure registers have to be used during SMMU configuration. 193 194 stream-match-mask: 195 $ref: /schemas/types.yaml#/definitions/uint32 196 description: | 197 For SMMUs supporting stream matching and using #iommu-cells = <1>, 198 specifies a mask of bits to ignore when matching stream IDs (e.g. this may 199 be programmed into the SMRn.MASK field of every stream match register 200 used). For cases where it is desirable to ignore some portion of every 201 Stream ID (e.g. for certain MMU-500 configurations given globally unique 202 input IDs). This property is not valid for SMMUs using stream indexing, or 203 using stream matching with #iommu-cells = <2>, and may be ignored if 204 present in such cases. 205 206 clock-names: 207 minItems: 1 208 maxItems: 7 209 210 clocks: 211 minItems: 1 212 maxItems: 7 213 214 power-domains: 215 minItems: 1 216 maxItems: 3 217 218 nvidia,memory-controller: 219 description: | 220 A phandle to the memory controller on NVIDIA Tegra186 and later SoCs. 221 The memory controller needs to be programmed with a mapping of memory 222 client IDs to ARM SMMU stream IDs. 223 224 If this property is absent, the mapping programmed by early firmware 225 will be used and it is not guaranteed that IOMMU translations will be 226 enabled for any given device. 227 $ref: /schemas/types.yaml#/definitions/phandle 228 229required: 230 - compatible 231 - reg 232 - '#global-interrupts' 233 - '#iommu-cells' 234 - interrupts 235 236additionalProperties: false 237 238allOf: 239 - if: 240 properties: 241 compatible: 242 contains: 243 enum: 244 - nvidia,tegra186-smmu 245 - nvidia,tegra194-smmu 246 - nvidia,tegra234-smmu 247 then: 248 properties: 249 reg: 250 minItems: 1 251 maxItems: 2 252 253 # The reference to the memory controller is required to ensure that the 254 # memory client to stream ID mapping can be done synchronously with the 255 # IOMMU attachment. 256 required: 257 - nvidia,memory-controller 258 else: 259 properties: 260 reg: 261 maxItems: 1 262 263 - if: 264 properties: 265 compatible: 266 contains: 267 enum: 268 - qcom,msm8998-smmu-v2 269 - qcom,sdm630-smmu-v2 270 then: 271 anyOf: 272 - properties: 273 clock-names: 274 items: 275 - const: bus 276 clocks: 277 items: 278 - description: bus clock required for downstream bus access and for 279 the smmu ptw 280 - properties: 281 clock-names: 282 items: 283 - const: iface 284 - const: mem 285 - const: mem_iface 286 clocks: 287 items: 288 - description: interface clock required to access smmu's registers 289 through the TCU's programming interface. 290 - description: bus clock required for memory access 291 - description: bus clock required for GPU memory access 292 - properties: 293 clock-names: 294 items: 295 - const: iface-mm 296 - const: iface-smmu 297 - const: bus-mm 298 - const: bus-smmu 299 clocks: 300 items: 301 - description: interface clock required to access mnoc's registers 302 through the TCU's programming interface. 303 - description: interface clock required to access smmu's registers 304 through the TCU's programming interface. 305 - description: bus clock required for downstream bus access 306 - description: bus clock required for the smmu ptw 307 308 - if: 309 properties: 310 compatible: 311 contains: 312 enum: 313 - qcom,msm8996-smmu-v2 314 - qcom,sc7180-smmu-v2 315 - qcom,sdm845-smmu-v2 316 then: 317 properties: 318 clock-names: 319 items: 320 - const: bus 321 - const: iface 322 323 clocks: 324 items: 325 - description: bus clock required for downstream bus access and for 326 the smmu ptw 327 - description: interface clock required to access smmu's registers 328 through the TCU's programming interface. 329 330 - if: 331 properties: 332 compatible: 333 contains: 334 const: qcom,sc7280-smmu-500 335 then: 336 properties: 337 clock-names: 338 items: 339 - const: gcc_gpu_memnoc_gfx_clk 340 - const: gcc_gpu_snoc_dvm_gfx_clk 341 - const: gpu_cc_ahb_clk 342 - const: gpu_cc_hlos1_vote_gpu_smmu_clk 343 - const: gpu_cc_cx_gmu_clk 344 - const: gpu_cc_hub_cx_int_clk 345 - const: gpu_cc_hub_aon_clk 346 347 clocks: 348 items: 349 - description: GPU memnoc_gfx clock 350 - description: GPU snoc_dvm_gfx clock 351 - description: GPU ahb clock 352 - description: GPU hlos1_vote_GPU smmu clock 353 - description: GPU cx_gmu clock 354 - description: GPU hub_cx_int clock 355 - description: GPU hub_aon clock 356 357 - if: 358 properties: 359 compatible: 360 contains: 361 enum: 362 - qcom,sm6350-smmu-v2 363 - qcom,sm8150-smmu-500 364 - qcom,sm8250-smmu-500 365 then: 366 properties: 367 clock-names: 368 items: 369 - const: ahb 370 - const: bus 371 - const: iface 372 373 clocks: 374 items: 375 - description: bus clock required for AHB bus access 376 - description: bus clock required for downstream bus access and for 377 the smmu ptw 378 - description: interface clock required to access smmu's registers 379 through the TCU's programming interface. 380 381 - if: 382 properties: 383 compatible: 384 items: 385 - enum: 386 - qcom,sm6115-smmu-500 387 - qcom,sm6125-smmu-500 388 - const: qcom,adreno-smmu 389 - const: qcom,smmu-500 390 - const: arm,mmu-500 391 then: 392 properties: 393 clock-names: 394 items: 395 - const: mem 396 - const: hlos 397 - const: iface 398 399 clocks: 400 items: 401 - description: GPU memory bus clock 402 - description: Voter clock required for HLOS SMMU access 403 - description: Interface clock required for register access 404 405 # Disallow clocks for all other platforms with specific compatibles 406 - if: 407 properties: 408 compatible: 409 contains: 410 enum: 411 - cavium,smmu-v2 412 - marvell,ap806-smmu-500 413 - nvidia,smmu-500 414 - qcom,qcm2290-smmu-500 415 - qcom,qdu1000-smmu-500 416 - qcom,sa8775p-smmu-500 417 - qcom,sc7180-smmu-500 418 - qcom,sc8180x-smmu-500 419 - qcom,sc8280xp-smmu-500 420 - qcom,sdm670-smmu-500 421 - qcom,sdm845-smmu-500 422 - qcom,sdx55-smmu-500 423 - qcom,sdx65-smmu-500 424 - qcom,sm6350-smmu-500 425 - qcom,sm6375-smmu-500 426 - qcom,sm8350-smmu-500 427 - qcom,sm8450-smmu-500 428 - qcom,sm8550-smmu-500 429 then: 430 properties: 431 clock-names: false 432 clocks: false 433 434 - if: 435 properties: 436 compatible: 437 contains: 438 const: qcom,sm6375-smmu-500 439 then: 440 properties: 441 power-domains: 442 items: 443 - description: SNoC MMU TBU RT GDSC 444 - description: SNoC MMU TBU NRT GDSC 445 - description: SNoC TURING MMU TBU0 GDSC 446 447 required: 448 - power-domains 449 else: 450 properties: 451 power-domains: 452 maxItems: 1 453 454examples: 455 - |+ 456 /* SMMU with stream matching or stream indexing */ 457 smmu1: iommu@ba5e0000 { 458 compatible = "arm,smmu-v1"; 459 reg = <0xba5e0000 0x10000>; 460 #global-interrupts = <2>; 461 interrupts = <0 32 4>, 462 <0 33 4>, 463 <0 34 4>, /* This is the first context interrupt */ 464 <0 35 4>, 465 <0 36 4>, 466 <0 37 4>; 467 #iommu-cells = <1>; 468 }; 469 470 /* device with two stream IDs, 0 and 7 */ 471 master1 { 472 iommus = <&smmu1 0>, 473 <&smmu1 7>; 474 }; 475 476 477 /* SMMU with stream matching */ 478 smmu2: iommu@ba5f0000 { 479 compatible = "arm,smmu-v1"; 480 reg = <0xba5f0000 0x10000>; 481 #global-interrupts = <2>; 482 interrupts = <0 38 4>, 483 <0 39 4>, 484 <0 40 4>, /* This is the first context interrupt */ 485 <0 41 4>, 486 <0 42 4>, 487 <0 43 4>; 488 #iommu-cells = <2>; 489 }; 490 491 /* device with stream IDs 0 and 7 */ 492 master2 { 493 iommus = <&smmu2 0 0>, 494 <&smmu2 7 0>; 495 }; 496 497 /* device with stream IDs 1, 17, 33 and 49 */ 498 master3 { 499 iommus = <&smmu2 1 0x30>; 500 }; 501 502 503 /* ARM MMU-500 with 10-bit stream ID input configuration */ 504 smmu3: iommu@ba600000 { 505 compatible = "arm,mmu-500", "arm,smmu-v2"; 506 reg = <0xba600000 0x10000>; 507 #global-interrupts = <2>; 508 interrupts = <0 44 4>, 509 <0 45 4>, 510 <0 46 4>, /* This is the first context interrupt */ 511 <0 47 4>, 512 <0 48 4>, 513 <0 49 4>; 514 #iommu-cells = <1>; 515 /* always ignore appended 5-bit TBU number */ 516 stream-match-mask = <0x7c00>; 517 }; 518 519 bus { 520 /* bus whose child devices emit one unique 10-bit stream 521 ID each, but may master through multiple SMMU TBUs */ 522 iommu-map = <0 &smmu3 0 0x400>; 523 524 525 }; 526 527 - |+ 528 /* Qcom's arm,smmu-v2 implementation */ 529 #include <dt-bindings/interrupt-controller/arm-gic.h> 530 #include <dt-bindings/interrupt-controller/irq.h> 531 smmu4: iommu@d00000 { 532 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; 533 reg = <0xd00000 0x10000>; 534 535 #global-interrupts = <1>; 536 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 537 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 539 #iommu-cells = <1>; 540 power-domains = <&mmcc 0>; 541 542 clocks = <&mmcc 123>, 543 <&mmcc 124>; 544 clock-names = "bus", "iface"; 545 }; 546