xref: /freebsd/sys/contrib/device-tree/Bindings/iommu/arm,smmu-v3.yaml (revision 5956d97f4b3204318ceb6aa9c77bd0bc6ea87a41) 
1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/iommu/arm,smmu-v3.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM SMMUv3 Architecture Implementation
8
9maintainers:
10  - Will Deacon <will@kernel.org>
11  - Robin Murphy <Robin.Murphy@arm.com>
12
13description: |+
14  The SMMUv3 architecture is a significant departure from previous
15  revisions, replacing the MMIO register interface with in-memory command
16  and event queues and adding support for the ATS and PRI components of
17  the PCIe specification.
18
19properties:
20  $nodename:
21    pattern: "^iommu@[0-9a-f]*"
22  compatible:
23    const: arm,smmu-v3
24
25  reg:
26    maxItems: 1
27
28  interrupts:
29    minItems: 1
30    maxItems: 4
31
32  interrupt-names:
33    oneOf:
34      - const: combined
35        description:
36          The combined interrupt is optional, and should only be provided if the
37          hardware supports just a single, combined interrupt line.
38          If provided, then the combined interrupt will be used in preference to
39          any others.
40      - minItems: 2
41        items:
42          - const: eventq     # Event Queue not empty
43          - const: gerror     # Global Error activated
44          - const: priq       # PRI Queue not empty
45          - const: cmdq-sync  # CMD_SYNC complete
46
47  '#iommu-cells':
48    const: 1
49
50  dma-coherent:
51    description: |
52      Present if page table walks made by the SMMU are cache coherent with the
53      CPU.
54
55      NOTE: this only applies to the SMMU itself, not masters connected
56      upstream of the SMMU.
57
58  msi-parent: true
59
60  hisilicon,broken-prefetch-cmd:
61    type: boolean
62    description: Avoid sending CMD_PREFETCH_* commands to the SMMU.
63
64  cavium,cn9900-broken-page1-regspace:
65    type: boolean
66    description:
67      Replaces all page 1 offsets used for EVTQ_PROD/CONS, PRIQ_PROD/CONS
68      register access with page 0 offsets. Set for Cavium ThunderX2 silicon that
69      doesn't support SMMU page1 register space.
70
71required:
72  - compatible
73  - reg
74  - '#iommu-cells'
75
76additionalProperties: false
77
78examples:
79  - |+
80    #include <dt-bindings/interrupt-controller/arm-gic.h>
81    #include <dt-bindings/interrupt-controller/irq.h>
82
83    iommu@2b400000 {
84            compatible = "arm,smmu-v3";
85            reg = <0x2b400000 0x20000>;
86            interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>,
87                         <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>,
88                         <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>,
89                         <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>;
90            interrupt-names = "eventq", "gerror", "priq", "cmdq-sync";
91            dma-coherent;
92            #iommu-cells = <1>;
93            msi-parent = <&its 0xff0000>;
94    };
95