xref: /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ti,sci-intr.txt (revision cfd6422a5217410fbd66f7a7a8a64d9d85e61229) 
1Texas Instruments K3 Interrupt Router
2=====================================
3
4The Interrupt Router (INTR) module provides a mechanism to mux M
5interrupt inputs to N interrupt outputs, where all M inputs are selectable
6to be driven per N output. An Interrupt Router can either handle edge triggered
7or level triggered interrupts and that is fixed in hardware.
8
9                                 Interrupt Router
10                             +----------------------+
11                             |  Inputs     Outputs  |
12        +-------+            | +------+    +-----+  |
13        | GPIO  |----------->| | irq0 |    |  0  |  |       Host IRQ
14        +-------+            | +------+    +-----+  |      controller
15                             |    .           .     |      +-------+
16        +-------+            |    .           .     |----->|  IRQ  |
17        | INTA  |----------->|    .           .     |      +-------+
18        +-------+            |    .        +-----+  |
19                             | +------+    |  N  |  |
20                             | | irqM |    +-----+  |
21                             | +------+             |
22                             |                      |
23                             +----------------------+
24
25There is one register per output (MUXCNTL_N) that controls the selection.
26Configuration of these MUXCNTL_N registers is done by a system controller
27(like the Device Memory and Security Controller on K3 AM654 SoC). System
28controller will keep track of the used and unused registers within the Router.
29Driver should request the system controller to get the range of GIC IRQs
30assigned to the requesting hosts. It is the drivers responsibility to keep
31track of Host IRQs.
32
33Communication between the host processor running an OS and the system
34controller happens through a protocol called TI System Control Interface
35(TISCI protocol). For more details refer:
36Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
37
38TISCI Interrupt Router Node:
39----------------------------
40Required Properties:
41- compatible:		Must be "ti,sci-intr".
42- ti,intr-trigger-type:	Should be one of the following:
43			1: If intr supports edge triggered interrupts.
44			4: If intr supports level triggered interrupts.
45- interrupt-controller:	Identifies the node as an interrupt controller
46- #interrupt-cells:	Specifies the number of cells needed to encode an
47			interrupt source. The value should be 2.
48			First cell should contain the TISCI device ID of source
49			Second cell should contain the interrupt source offset
50			within the device.
51- ti,sci:		Phandle to TI-SCI compatible System controller node.
52- ti,sci-dst-id:	TISCI device ID of the destination IRQ controller.
53- ti,sci-rm-range-girq:	Array of TISCI subtype ids representing the host irqs
54			assigned to this interrupt router. Each subtype id
55			corresponds to a range of host irqs.
56
57For more details on TISCI IRQ resource management refer:
58http://downloads.ti.com/tisci/esd/latest/2_tisci_msgs/rm/rm_irq.html
59
60Example:
61--------
62The following example demonstrates both interrupt router node and the consumer
63node(main gpio) on the AM654 SoC:
64
65main_intr: interrupt-controller0 {
66	compatible = "ti,sci-intr";
67	ti,intr-trigger-type = <1>;
68	interrupt-controller;
69	interrupt-parent = <&gic500>;
70	#interrupt-cells = <2>;
71	ti,sci = <&dmsc>;
72	ti,sci-dst-id = <56>;
73	ti,sci-rm-range-girq = <0x1>;
74};
75
76main_gpio0: gpio@600000 {
77	...
78	interrupt-parent = <&main_intr>;
79	interrupts = <57 256>, <57 257>, <57 258>,
80		     <57 259>, <57 260>, <57 261>;
81	...
82};
83