1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/interrupt-controller/ti,sci-inta.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Texas Instruments K3 Interrupt Aggregator 8 9maintainers: 10 - Lokesh Vutla <lokeshvutla@ti.com> 11 12allOf: 13 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml# 14 15description: | 16 The Interrupt Aggregator (INTA) provides a centralized machine 17 which handles the termination of system events to that they can 18 be coherently processed by the host(s) in the system. A maximum 19 of 64 events can be mapped to a single interrupt. 20 21 Interrupt Aggregator 22 +-----------------------------------------+ 23 | Intmap VINT | 24 | +--------------+ +------------+ | 25 m ------>| | vint | bit | | 0 |.....|63| vint0 | 26 . | +--------------+ +------------+ | +------+ 27 . | . . | | HOST | 28 Globalevents ------>| . . |----->| IRQ | 29 . | . . | | CTRL | 30 . | . . | +------+ 31 n ------>| +--------------+ +------------+ | 32 | | vint | bit | | 0 |.....|63| vintx | 33 | +--------------+ +------------+ | 34 | | 35 | Unmap | 36 | +--------------+ | 37 Unmapped events ---->| | umapidx |-------------------------> Globalevents 38 | +--------------+ | 39 | | 40 +-----------------------------------------+ 41 42 Configuration of these Intmap registers that maps global events to vint is 43 done by a system controller (like the Device Memory and Security Controller 44 on AM654 SoC). Driver should request the system controller to get the range 45 of global events and vints assigned to the requesting host. Management 46 of these requested resources should be handled by driver and requests 47 system controller to map specific global event to vint, bit pair. 48 49 Communication between the host processor running an OS and the system 50 controller happens through a protocol called TI System Control Interface 51 (TISCI protocol). 52 53properties: 54 compatible: 55 const: ti,sci-inta 56 57 reg: 58 maxItems: 1 59 60 interrupt-controller: true 61 62 msi-controller: true 63 64 ti,interrupt-ranges: 65 $ref: /schemas/types.yaml#/definitions/uint32-matrix 66 description: | 67 Interrupt ranges that converts the INTA output hw irq numbers 68 to parents's input interrupt numbers. 69 items: 70 items: 71 - description: | 72 "output_irq" specifies the base for inta output irq 73 - description: | 74 "parent's input irq" specifies the base for parent irq 75 - description: | 76 "limit" specifies the limit for translation 77 78 ti,unmapped-event-sources: 79 $ref: /schemas/types.yaml#/definitions/phandle-array 80 items: 81 maxItems: 1 82 description: 83 Array of phandles to DMA controllers where the unmapped events originate. 84 85required: 86 - compatible 87 - reg 88 - interrupt-controller 89 - msi-controller 90 - ti,sci 91 - ti,sci-dev-id 92 - ti,interrupt-ranges 93 94unevaluatedProperties: false 95 96examples: 97 - | 98 bus { 99 #address-cells = <2>; 100 #size-cells = <2>; 101 102 main_udmass_inta: msi-controller@33d00000 { 103 compatible = "ti,sci-inta"; 104 reg = <0x0 0x33d00000 0x0 0x100000>; 105 interrupt-controller; 106 msi-controller; 107 interrupt-parent = <&main_navss_intr>; 108 ti,sci = <&dmsc>; 109 ti,sci-dev-id = <179>; 110 ti,interrupt-ranges = <0 0 256>; 111 }; 112 }; 113