xref: /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml (revision e32fecd0c2c3ee37c47ee100f169e7eb0282a873) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2# Copyright (C) 2020 SiFive, Inc.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: SiFive Platform-Level Interrupt Controller (PLIC)
9
10description:
11  SiFive SoCs and other RISC-V SoCs include an implementation of the
12  Platform-Level Interrupt Controller (PLIC) high-level specification in
13  the RISC-V Privileged Architecture specification. The PLIC connects all
14  external interrupts in the system to all hart contexts in the system, via
15  the external interrupt source in each hart.
16
17  A hart context is a privilege mode in a hardware execution thread. For example,
18  in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
19  privilege modes per hart; machine mode and supervisor mode.
20
21  Each interrupt can be enabled on per-context basis. Any context can claim
22  a pending enabled interrupt and then release it once it has been handled.
23
24  Each interrupt has a configurable priority. Higher priority interrupts are
25  serviced first.  Each context can specify a priority threshold. Interrupts
26  with priority below this threshold will not cause the PLIC to raise its
27  interrupt line leading to the context.
28
29  The PLIC supports both edge-triggered and level-triggered interrupts. For
30  edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges
31  seen while an interrupt handler is active; the PLIC may either queue them or
32  ignore them. In the first case, handlers are oblivious to the trigger type, so
33  it is not included in the interrupt specifier. In the second case, software
34  needs to know the trigger type, so it can reorder the interrupt flow to avoid
35  missing interrupts. This special handling is needed by at least the Renesas
36  RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC.
37
38  While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
39  "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
40  contains a specific memory layout, which is documented in chapter 8 of the
41  SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
42
43  The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the
44  T-HEAD PLIC implementation requires setting a delegation bit to allow access
45  from S-mode. So add thead,c900-plic to distinguish them.
46
47maintainers:
48  - Sagar Kadam <sagar.kadam@sifive.com>
49  - Paul Walmsley  <paul.walmsley@sifive.com>
50  - Palmer Dabbelt <palmer@dabbelt.com>
51
52properties:
53  compatible:
54    oneOf:
55      - items:
56          - enum:
57              - renesas,r9a07g043-plic
58          - const: andestech,nceplic100
59      - items:
60          - enum:
61              - sifive,fu540-c000-plic
62              - starfive,jh7100-plic
63              - canaan,k210-plic
64          - const: sifive,plic-1.0.0
65      - items:
66          - enum:
67              - allwinner,sun20i-d1-plic
68          - const: thead,c900-plic
69
70  reg:
71    maxItems: 1
72
73  '#address-cells':
74    const: 0
75
76  '#interrupt-cells': true
77
78  interrupt-controller: true
79
80  interrupts-extended:
81    minItems: 1
82    maxItems: 15872
83    description:
84      Specifies which contexts are connected to the PLIC, with "-1" specifying
85      that a context is not present. Each node pointed to should be a
86      riscv,cpu-intc node, which has a riscv node as parent.
87
88  riscv,ndev:
89    $ref: "/schemas/types.yaml#/definitions/uint32"
90    description:
91      Specifies how many external interrupts are supported by this controller.
92
93  clocks: true
94
95  power-domains: true
96
97  resets: true
98
99required:
100  - compatible
101  - '#address-cells'
102  - '#interrupt-cells'
103  - interrupt-controller
104  - reg
105  - interrupts-extended
106  - riscv,ndev
107
108allOf:
109  - if:
110      properties:
111        compatible:
112          contains:
113            enum:
114              - andestech,nceplic100
115              - thead,c900-plic
116
117    then:
118      properties:
119        '#interrupt-cells':
120          const: 2
121
122    else:
123      properties:
124        '#interrupt-cells':
125          const: 1
126
127  - if:
128      properties:
129        compatible:
130          contains:
131            const: renesas,r9a07g043-plic
132
133    then:
134      properties:
135        clocks:
136          maxItems: 1
137
138        power-domains:
139          maxItems: 1
140
141        resets:
142          maxItems: 1
143
144      required:
145        - clocks
146        - power-domains
147        - resets
148
149additionalProperties: false
150
151examples:
152  - |
153    plic: interrupt-controller@c000000 {
154      #address-cells = <0>;
155      #interrupt-cells = <1>;
156      compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
157      interrupt-controller;
158      interrupts-extended = <&cpu0_intc 11>,
159                            <&cpu1_intc 11>, <&cpu1_intc 9>,
160                            <&cpu2_intc 11>, <&cpu2_intc 9>,
161                            <&cpu3_intc 11>, <&cpu3_intc 9>,
162                            <&cpu4_intc 11>, <&cpu4_intc 9>;
163      reg = <0xc000000 0x4000000>;
164      riscv,ndev = <10>;
165    };
166