xref: /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml (revision b64c5a0ace59af62eff52bfe110a521dc73c937b) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2# Copyright (C) 2020 SiFive, Inc.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: SiFive Platform-Level Interrupt Controller (PLIC)
9
10description:
11  SiFive SoCs and other RISC-V SoCs include an implementation of the
12  Platform-Level Interrupt Controller (PLIC) high-level specification in
13  the RISC-V Privileged Architecture specification. The PLIC connects all
14  external interrupts in the system to all hart contexts in the system, via
15  the external interrupt source in each hart.
16
17  A hart context is a privilege mode in a hardware execution thread. For example,
18  in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
19  privilege modes per hart; machine mode and supervisor mode.
20
21  Each interrupt can be enabled on per-context basis. Any context can claim
22  a pending enabled interrupt and then release it once it has been handled.
23
24  Each interrupt has a configurable priority. Higher priority interrupts are
25  serviced first.  Each context can specify a priority threshold. Interrupts
26  with priority below this threshold will not cause the PLIC to raise its
27  interrupt line leading to the context.
28
29  The PLIC supports both edge-triggered and level-triggered interrupts. For
30  edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges
31  seen while an interrupt handler is active; the PLIC may either queue them or
32  ignore them. In the first case, handlers are oblivious to the trigger type, so
33  it is not included in the interrupt specifier. In the second case, software
34  needs to know the trigger type, so it can reorder the interrupt flow to avoid
35  missing interrupts. This special handling is needed by at least the Renesas
36  RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC.
37
38  While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
39  "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
40  contains a specific memory layout, which is documented in chapter 8 of the
41  SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
42
43  The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the
44  T-HEAD PLIC implementation requires setting a delegation bit to allow access
45  from S-mode. So add thead,c900-plic to distinguish them.
46
47maintainers:
48  - Paul Walmsley  <paul.walmsley@sifive.com>
49  - Palmer Dabbelt <palmer@dabbelt.com>
50
51properties:
52  compatible:
53    oneOf:
54      - items:
55          - enum:
56              - renesas,r9a07g043-plic
57          - const: andestech,nceplic100
58      - items:
59          - enum:
60              - canaan,k210-plic
61              - sifive,fu540-c000-plic
62              - starfive,jh7100-plic
63              - starfive,jh7110-plic
64          - const: sifive,plic-1.0.0
65      - items:
66          - enum:
67              - allwinner,sun20i-d1-plic
68              - sophgo,cv1800b-plic
69              - sophgo,cv1812h-plic
70              - sophgo,sg2042-plic
71              - thead,th1520-plic
72          - const: thead,c900-plic
73      - items:
74          - const: sifive,plic-1.0.0
75          - const: riscv,plic0
76        deprecated: true
77        description: For the QEMU virt machine only
78
79  reg:
80    maxItems: 1
81
82  '#address-cells':
83    const: 0
84
85  '#interrupt-cells': true
86
87  interrupt-controller: true
88
89  interrupts-extended:
90    minItems: 1
91    maxItems: 15872
92    description:
93      Specifies which contexts are connected to the PLIC, with "-1" specifying
94      that a context is not present. Each node pointed to should be a
95      riscv,cpu-intc node, which has a riscv node as parent.
96
97  riscv,ndev:
98    $ref: /schemas/types.yaml#/definitions/uint32
99    description:
100      Specifies how many external interrupts are supported by this controller.
101
102  clocks: true
103
104  power-domains: true
105
106  resets: true
107
108required:
109  - compatible
110  - '#address-cells'
111  - '#interrupt-cells'
112  - interrupt-controller
113  - reg
114  - interrupts-extended
115  - riscv,ndev
116
117allOf:
118  - if:
119      properties:
120        compatible:
121          contains:
122            enum:
123              - andestech,nceplic100
124              - thead,c900-plic
125
126    then:
127      properties:
128        '#interrupt-cells':
129          const: 2
130
131    else:
132      properties:
133        '#interrupt-cells':
134          const: 1
135
136  - if:
137      properties:
138        compatible:
139          contains:
140            const: renesas,r9a07g043-plic
141
142    then:
143      properties:
144        clocks:
145          maxItems: 1
146
147        power-domains:
148          maxItems: 1
149
150        resets:
151          maxItems: 1
152
153      required:
154        - clocks
155        - power-domains
156        - resets
157
158additionalProperties: false
159
160examples:
161  - |
162    plic: interrupt-controller@c000000 {
163      #address-cells = <0>;
164      #interrupt-cells = <1>;
165      compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
166      interrupt-controller;
167      interrupts-extended = <&cpu0_intc 11>,
168                            <&cpu1_intc 11>, <&cpu1_intc 9>,
169                            <&cpu2_intc 11>, <&cpu2_intc 9>,
170                            <&cpu3_intc 11>, <&cpu3_intc 9>,
171                            <&cpu4_intc 11>, <&cpu4_intc 9>;
172      reg = <0xc000000 0x4000000>;
173      riscv,ndev = <10>;
174    };
175