1SiFive Platform-Level Interrupt Controller (PLIC) 2------------------------------------------------- 3 4SiFive SOCs include an implementation of the Platform-Level Interrupt Controller 5(PLIC) high-level specification in the RISC-V Privileged Architecture 6specification. The PLIC connects all external interrupts in the system to all 7hart contexts in the system, via the external interrupt source in each hart. 8 9A hart context is a privilege mode in a hardware execution thread. For example, 10in an 4 core system with 2-way SMT, you have 8 harts and probably at least two 11privilege modes per hart; machine mode and supervisor mode. 12 13Each interrupt can be enabled on per-context basis. Any context can claim 14a pending enabled interrupt and then release it once it has been handled. 15 16Each interrupt has a configurable priority. Higher priority interrupts are 17serviced first. Each context can specify a priority threshold. Interrupts 18with priority below this threshold will not cause the PLIC to raise its 19interrupt line leading to the context. 20 21While the PLIC supports both edge-triggered and level-triggered interrupts, 22interrupt handlers are oblivious to this distinction and therefore it is not 23specified in the PLIC device-tree binding. 24 25While the RISC-V ISA doesn't specify a memory layout for the PLIC, the 26"sifive,plic-1.0.0" device is a concrete implementation of the PLIC that 27contains a specific memory layout, which is documented in chapter 8 of the 28SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>. 29 30Required properties: 31- compatible : "sifive,plic-1.0.0" and a string identifying the actual 32 detailed implementation in case that specific bugs need to be worked around. 33- #address-cells : should be <0> or more. 34- #interrupt-cells : should be <1> or more. 35- interrupt-controller : Identifies the node as an interrupt controller. 36- reg : Should contain 1 register range (address and length). 37- interrupts-extended : Specifies which contexts are connected to the PLIC, 38 with "-1" specifying that a context is not present. Each node pointed 39 to should be a riscv,cpu-intc node, which has a riscv node as parent. 40- riscv,ndev: Specifies how many external interrupts are supported by 41 this controller. 42 43Example: 44 45 plic: interrupt-controller@c000000 { 46 #address-cells = <0>; 47 #interrupt-cells = <1>; 48 compatible = "sifive,plic-1.0.0", "sifive,fu540-c000-plic"; 49 interrupt-controller; 50 interrupts-extended = < 51 &cpu0-intc 11 52 &cpu1-intc 11 &cpu1-intc 9 53 &cpu2-intc 11 &cpu2-intc 9 54 &cpu3-intc 11 &cpu3-intc 9 55 &cpu4-intc 11 &cpu4-intc 9>; 56 reg = <0xc000000 0x4000000>; 57 riscv,ndev = <10>; 58 }; 59