1RISC-V Hart-Level Interrupt Controller (HLIC) 2--------------------------------------------- 3 4RISC-V cores include Control Status Registers (CSRs) which are local to each 5CPU core (HART in RISC-V terminology) and can be read or written by software. 6Some of these CSRs are used to control local interrupts connected to the core. 7Every interrupt is ultimately routed through a hart's HLIC before it 8interrupts that hart. 9 10The RISC-V supervisor ISA manual specifies three interrupt sources that are 11attached to every HLIC: software interrupts, the timer interrupt, and external 12interrupts. Software interrupts are used to send IPIs between cores. The 13timer interrupt comes from an architecturally mandated real-time timer that is 14controlled via Supervisor Binary Interface (SBI) calls and CSR reads. External 15interrupts connect all other device interrupts to the HLIC, which are routed 16via the platform-level interrupt controller (PLIC). 17 18All RISC-V systems that conform to the supervisor ISA specification are 19required to have a HLIC with these three interrupt sources present. Since the 20interrupt map is defined by the ISA it's not listed in the HLIC's device tree 21entry, though external interrupt controllers (like the PLIC, for example) will 22need to define how their interrupts map to the relevant HLICs. This means 23a PLIC interrupt property will typically list the HLICs for all present HARTs 24in the system. 25 26Required properties: 27- compatible : "riscv,cpu-intc" 28- #interrupt-cells : should be <1>. The interrupt sources are defined by the 29 RISC-V supervisor ISA manual, with only the following three interrupts being 30 defined for supervisor mode: 31 - Source 1 is the supervisor software interrupt, which can be sent by an SBI 32 call and is reserved for use by software. 33 - Source 5 is the supervisor timer interrupt, which can be configured by 34 SBI calls and implements a one-shot timer. 35 - Source 9 is the supervisor external interrupt, which chains to all other 36 device interrupts. 37- interrupt-controller : Identifies the node as an interrupt controller 38 39Furthermore, this interrupt-controller MUST be embedded inside the cpu 40definition of the hart whose CSRs control these local interrupts. 41 42An example device tree entry for a HLIC is show below. 43 44 cpu1: cpu@1 { 45 compatible = "riscv"; 46 ... 47 cpu1-intc: interrupt-controller { 48 #interrupt-cells = <1>; 49 compatible = "sifive,fu540-c000-cpu-intc", "riscv,cpu-intc"; 50 interrupt-controller; 51 }; 52 }; 53