1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/interrupt-controller/renesas,rzg2l-irqc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Renesas RZ/G2L (and alike SoC's) Interrupt Controller (IA55) 8 9maintainers: 10 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> 11 - Geert Uytterhoeven <geert+renesas@glider.be> 12 13description: | 14 IA55 performs various interrupt controls including synchronization for the external 15 interrupts of NMI, IRQ, and GPIOINT and the interrupts of the built-in peripheral 16 interrupts output by each IP. And it notifies the interrupt to the GIC 17 - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts 18 - GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts 19 - NMI edge select (NMI is not treated as NMI exception and supports fall edge and 20 stand-up edge detection interrupts) 21 22properties: 23 compatible: 24 items: 25 - enum: 26 - renesas,r9a07g043u-irqc # RZ/G2UL 27 - renesas,r9a07g044-irqc # RZ/G2{L,LC} 28 - renesas,r9a07g054-irqc # RZ/V2L 29 - renesas,r9a08g045-irqc # RZ/G3S 30 - const: renesas,rzg2l-irqc 31 32 '#interrupt-cells': 33 description: The first cell should contain a macro RZG2L_{NMI,IRQX} included in the 34 include/dt-bindings/interrupt-controller/irqc-rzg2l.h and the second 35 cell is used to specify the flag. 36 const: 2 37 38 '#address-cells': 39 const: 0 40 41 interrupt-controller: true 42 43 reg: 44 maxItems: 1 45 46 interrupts: 47 minItems: 41 48 items: 49 - description: NMI interrupt 50 - description: IRQ0 interrupt 51 - description: IRQ1 interrupt 52 - description: IRQ2 interrupt 53 - description: IRQ3 interrupt 54 - description: IRQ4 interrupt 55 - description: IRQ5 interrupt 56 - description: IRQ6 interrupt 57 - description: IRQ7 interrupt 58 - description: GPIO interrupt, TINT0 59 - description: GPIO interrupt, TINT1 60 - description: GPIO interrupt, TINT2 61 - description: GPIO interrupt, TINT3 62 - description: GPIO interrupt, TINT4 63 - description: GPIO interrupt, TINT5 64 - description: GPIO interrupt, TINT6 65 - description: GPIO interrupt, TINT7 66 - description: GPIO interrupt, TINT8 67 - description: GPIO interrupt, TINT9 68 - description: GPIO interrupt, TINT10 69 - description: GPIO interrupt, TINT11 70 - description: GPIO interrupt, TINT12 71 - description: GPIO interrupt, TINT13 72 - description: GPIO interrupt, TINT14 73 - description: GPIO interrupt, TINT15 74 - description: GPIO interrupt, TINT16 75 - description: GPIO interrupt, TINT17 76 - description: GPIO interrupt, TINT18 77 - description: GPIO interrupt, TINT19 78 - description: GPIO interrupt, TINT20 79 - description: GPIO interrupt, TINT21 80 - description: GPIO interrupt, TINT22 81 - description: GPIO interrupt, TINT23 82 - description: GPIO interrupt, TINT24 83 - description: GPIO interrupt, TINT25 84 - description: GPIO interrupt, TINT26 85 - description: GPIO interrupt, TINT27 86 - description: GPIO interrupt, TINT28 87 - description: GPIO interrupt, TINT29 88 - description: GPIO interrupt, TINT30 89 - description: GPIO interrupt, TINT31 90 - description: Bus error interrupt 91 92 interrupt-names: 93 minItems: 41 94 items: 95 - const: nmi 96 - const: irq0 97 - const: irq1 98 - const: irq2 99 - const: irq3 100 - const: irq4 101 - const: irq5 102 - const: irq6 103 - const: irq7 104 - const: tint0 105 - const: tint1 106 - const: tint2 107 - const: tint3 108 - const: tint4 109 - const: tint5 110 - const: tint6 111 - const: tint7 112 - const: tint8 113 - const: tint9 114 - const: tint10 115 - const: tint11 116 - const: tint12 117 - const: tint13 118 - const: tint14 119 - const: tint15 120 - const: tint16 121 - const: tint17 122 - const: tint18 123 - const: tint19 124 - const: tint20 125 - const: tint21 126 - const: tint22 127 - const: tint23 128 - const: tint24 129 - const: tint25 130 - const: tint26 131 - const: tint27 132 - const: tint28 133 - const: tint29 134 - const: tint30 135 - const: tint31 136 - const: bus-err 137 138 clocks: 139 maxItems: 2 140 141 clock-names: 142 items: 143 - const: clk 144 - const: pclk 145 146 power-domains: 147 maxItems: 1 148 149 resets: 150 maxItems: 1 151 152required: 153 - compatible 154 - '#interrupt-cells' 155 - '#address-cells' 156 - interrupt-controller 157 - reg 158 - interrupts 159 - clocks 160 - clock-names 161 - power-domains 162 - resets 163 164allOf: 165 - $ref: /schemas/interrupt-controller.yaml# 166 167 - if: 168 properties: 169 compatible: 170 contains: 171 enum: 172 - renesas,r9a07g043u-irqc 173 - renesas,r9a08g045-irqc 174 then: 175 properties: 176 interrupts: 177 minItems: 42 178 interrupt-names: 179 minItems: 42 180 required: 181 - interrupt-names 182 183unevaluatedProperties: false 184 185examples: 186 - | 187 #include <dt-bindings/interrupt-controller/arm-gic.h> 188 #include <dt-bindings/clock/r9a07g044-cpg.h> 189 190 irqc: interrupt-controller@110a0000 { 191 compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc"; 192 reg = <0x110a0000 0x10000>; 193 #interrupt-cells = <2>; 194 #address-cells = <0>; 195 interrupt-controller; 196 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; 237 interrupt-names = "nmi", 238 "irq0", "irq1", "irq2", "irq3", 239 "irq4", "irq5", "irq6", "irq7", 240 "tint0", "tint1", "tint2", "tint3", 241 "tint4", "tint5", "tint6", "tint7", 242 "tint8", "tint9", "tint10", "tint11", 243 "tint12", "tint13", "tint14", "tint15", 244 "tint16", "tint17", "tint18", "tint19", 245 "tint20", "tint21", "tint22", "tint23", 246 "tint24", "tint25", "tint26", "tint27", 247 "tint28", "tint29", "tint30", "tint31"; 248 clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>, 249 <&cpg CPG_MOD R9A07G044_IA55_PCLK>; 250 clock-names = "clk", "pclk"; 251 power-domains = <&cpg>; 252 resets = <&cpg R9A07G044_IA55_RESETN>; 253 }; 254