xref: /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/qcom,pdc.yaml (revision a03411e84728e9b267056fd31c7d1d9d1dc1b01e) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interrupt-controller/qcom,pdc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: PDC interrupt controller
8
9maintainers:
10  - Bjorn Andersson <bjorn.andersson@linaro.org>
11
12description: |
13  Qualcomm Technologies Inc. SoCs based on the RPM Hardened architecture have a
14  Power Domain Controller (PDC) that is on always-on domain. In addition to
15  providing power control for the power domains, the hardware also has an
16  interrupt controller that can be used to help detect edge low interrupts as
17  well detect interrupts when the GIC is non-operational.
18
19  GIC is parent interrupt controller at the highest level. Platform interrupt
20  controller PDC is next in hierarchy, followed by others. Drivers requiring
21  wakeup capabilities of their device interrupts routed through the PDC, must
22  specify PDC as their interrupt controller and request the PDC port associated
23  with the GIC interrupt. See example below.
24
25properties:
26  compatible:
27    items:
28      - enum:
29          - qcom,qdu1000-pdc
30          - qcom,sa8775p-pdc
31          - qcom,sc7180-pdc
32          - qcom,sc7280-pdc
33          - qcom,sc8280xp-pdc
34          - qcom,sdm845-pdc
35          - qcom,sdx55-pdc
36          - qcom,sdx65-pdc
37          - qcom,sm6350-pdc
38          - qcom,sm8150-pdc
39          - qcom,sm8250-pdc
40          - qcom,sm8350-pdc
41          - qcom,sm8450-pdc
42      - const: qcom,pdc
43
44  reg:
45    minItems: 1
46    items:
47      - description: PDC base register region
48      - description: Edge or Level config register for SPI interrupts
49
50  '#interrupt-cells':
51    const: 2
52
53  interrupt-controller: true
54
55  qcom,pdc-ranges:
56    $ref: /schemas/types.yaml#/definitions/uint32-matrix
57    minItems: 1
58    maxItems: 128 # no hard limit
59    items:
60      items:
61        - description: starting PDC port
62        - description: GIC hwirq number for the PDC port
63        - description: number of interrupts in sequence
64    description: |
65      Specifies the PDC pin offset and the number of PDC ports.
66      The tuples indicates the valid mapping of valid PDC ports
67      and their hwirq mapping.
68
69required:
70  - compatible
71  - reg
72  - '#interrupt-cells'
73  - interrupt-controller
74  - qcom,pdc-ranges
75
76additionalProperties: false
77
78examples:
79  - |
80    #include <dt-bindings/interrupt-controller/irq.h>
81
82    pdc: interrupt-controller@b220000 {
83        compatible = "qcom,sdm845-pdc", "qcom,pdc";
84        reg = <0xb220000 0x30000>;
85        qcom,pdc-ranges = <0 512 94>, <94 641 15>, <115 662 7>;
86        #interrupt-cells = <2>;
87        interrupt-parent = <&intc>;
88        interrupt-controller;
89    };
90
91    wake-device {
92        interrupts-extended = <&pdc 2 IRQ_TYPE_LEVEL_HIGH>;
93    };
94