1Microchip PIC32 Interrupt Controller 2==================================== 3 4The Microchip PIC32 contains an Enhanced Vectored Interrupt Controller (EVIC). 5It handles all internal and external interrupts. This controller exists outside 6of the CPU and is the arbitrator of all interrupts (including interrupts from 7the CPU itself) before they are presented to the CPU. 8 9External interrupts have a software configurable edge polarity. Non external 10interrupts have a type and polarity that is determined by the source of the 11interrupt. 12 13Required properties 14------------------- 15 16- compatible: Should be "microchip,pic32mzda-evic" 17- reg: Specifies physical base address and size of register range. 18- interrupt-controller: Identifies the node as an interrupt controller. 19- #interrupt cells: Specifies the number of cells used to encode an interrupt 20 source connected to this controller. The value shall be 2 and interrupt 21 descriptor shall have the following format: 22 23 <hw_irq irq_type> 24 25 hw_irq - represents the hardware interrupt number as in the data sheet. 26 irq_type - is used to describe the type and polarity of an interrupt. For 27 internal interrupts use IRQ_TYPE_EDGE_RISING for non persistent interrupts and 28 IRQ_TYPE_LEVEL_HIGH for persistent interrupts. For external interrupts use 29 IRQ_TYPE_EDGE_RISING or IRQ_TYPE_EDGE_FALLING to select the desired polarity. 30 31Optional properties 32------------------- 33- microchip,external-irqs: u32 array of external interrupts with software 34 polarity configuration. This array corresponds to the bits in the INTCON 35 SFR. 36 37Example 38------- 39 40evic: interrupt-controller@1f810000 { 41 compatible = "microchip,pic32mzda-evic"; 42 interrupt-controller; 43 #interrupt-cells = <2>; 44 reg = <0x1f810000 0x1000>; 45 microchip,external-irqs = <3 8 13 18 23>; 46}; 47 48Each device/peripheral must request its interrupt line with the associated type 49and polarity. 50 51Internal interrupt DTS snippet 52------------------------------ 53 54device@1f800000 { 55 ... 56 interrupts = <113 IRQ_TYPE_LEVEL_HIGH>; 57 ... 58}; 59 60External interrupt DTS snippet 61------------------------------ 62 63device@1f800000 { 64 ... 65 interrupts = <3 IRQ_TYPE_EDGE_RISING>; 66 ... 67}; 68