1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/interrupt-controller/intel,ce4100-ioapic.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Intel I/O Advanced Programmable Interrupt Controller (IO APIC) 8 9maintainers: 10 - Rahul Tanwar <rtanwar@maxlinear.com> 11 12description: | 13 Intel's Advanced Programmable Interrupt Controller (APIC) is a 14 family of interrupt controllers. The APIC is a split 15 architecture design, with a local component (LAPIC) integrated 16 into the processor itself and an external I/O APIC. Local APIC 17 (lapic) receives interrupts from the processor's interrupt pins, 18 from internal sources and from an external I/O APIC (ioapic). 19 And it sends these to the processor core for handling. 20 See [1] Chapter 8 for more details. 21 22 Many of the Intel's generic devices like hpet, ioapic, lapic have 23 the ce4100 name in their compatible property names because they 24 first appeared in CE4100 SoC. 25 26 This schema defines bindings for I/O APIC interrupt controller. 27 28 [1] https://pdos.csail.mit.edu/6.828/2008/readings/ia32/IA32-3A.pdf 29 30properties: 31 compatible: 32 const: intel,ce4100-ioapic 33 34 reg: 35 maxItems: 1 36 37 interrupt-controller: true 38 39 '#interrupt-cells': 40 const: 2 41 42 interrupts: 43 maxItems: 1 44 45required: 46 - compatible 47 - reg 48 - interrupt-controller 49 - '#interrupt-cells' 50 51additionalProperties: false 52 53examples: 54 - | 55 ioapic1: interrupt-controller@fec00000 { 56 compatible = "intel,ce4100-ioapic"; 57 reg = <0xfec00000 0x1000>; 58 interrupt-controller; 59 #interrupt-cells = <2>; 60 }; 61