xref: /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/fsl,irqsteer.yaml (revision cfd6422a5217410fbd66f7a7a8a64d9d85e61229) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interrupt-controller/fsl,irqsteer.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Freescale IRQSTEER Interrupt Multiplexer
8
9maintainers:
10  - Lucas Stach <l.stach@pengutronix.de>
11
12properties:
13  compatible:
14    enum:
15      - fsl,imx8m-irqsteer
16      - fsl,imx-irqsteer
17
18  reg:
19    maxItems: 1
20
21  interrupts:
22    description: |
23      should contain the up to 8 parent interrupt lines used to multiplex
24      the input interrupts. They should be specified sequentially from
25      output 0 to 7.
26    items:
27      - description: output interrupt 0
28      - description: output interrupt 1
29      - description: output interrupt 2
30      - description: output interrupt 3
31      - description: output interrupt 4
32      - description: output interrupt 5
33      - description: output interrupt 6
34      - description: output interrupt 7
35    minItems: 1
36    maxItems: 8
37
38  clocks:
39    maxItems: 1
40
41  clock-names:
42    const: ipg
43
44  interrupt-controller: true
45
46  "#interrupt-cells":
47    const: 1
48
49  fsl,channel:
50    $ref: '/schemas/types.yaml#/definitions/uint32'
51    description: |
52      u32 value representing the output channel that all input IRQs should be
53      steered into.
54
55  fsl,num-irqs:
56    $ref: '/schemas/types.yaml#/definitions/uint32'
57    description: |
58      u32 value representing the number of input interrupts of this channel,
59      should be multiple of 32 input interrupts and up to 512 interrupts.
60
61required:
62  - compatible
63  - reg
64  - interrupts
65  - clocks
66  - clock-names
67  - interrupt-controller
68  - "#interrupt-cells"
69  - fsl,channel
70  - fsl,num-irqs
71
72additionalProperties: false
73
74examples:
75  - |
76    #include <dt-bindings/clock/imx8mq-clock.h>
77    #include <dt-bindings/interrupt-controller/arm-gic.h>
78
79    interrupt-controller@32e2d000 {
80        compatible = "fsl,imx-irqsteer";
81        reg = <0x32e2d000 0x1000>;
82        interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
83        clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
84        clock-names = "ipg";
85        fsl,channel = <0>;
86        fsl,num-irqs = <64>;
87        interrupt-controller;
88        #interrupt-cells = <1>;
89    };
90