1TB10x Top Level Interrupt Controller 2==================================== 3 4The Abilis TB10x SOC contains a custom interrupt controller. It performs 5one-to-one mapping of external interrupt sources to CPU interrupts and 6provides support for reconfigurable trigger modes. 7 8Required properties 9------------------- 10 11- compatible: Should be "abilis,tb10x-ictl" 12- reg: specifies physical base address and size of register range. 13- interrupt-congroller: Identifies the node as an interrupt controller. 14- #interrupt cells: Specifies the number of cells used to encode an interrupt 15 source connected to this controller. The value shall be 2. 16- interrupts: Specifies the list of interrupt lines which are handled by 17 the interrupt controller in the parent controller's notation. Interrupts 18 are mapped one-to-one to parent interrupts. 19 20Example 21------- 22 23intc: interrupt-controller { /* Parent interrupt controller */ 24 interrupt-controller; 25 #interrupt-cells = <1>; /* For example below */ 26 /* ... */ 27}; 28 29tb10x_ictl: pic@2000 { /* TB10x interrupt controller */ 30 compatible = "abilis,tb10x-ictl"; 31 reg = <0x2000 0x20>; 32 interrupt-controller; 33 #interrupt-cells = <2>; 34 interrupt-parent = <&intc>; 35 interrupts = <5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 36 20 21 22 23 24 25 26 27 28 29 30 31>; 37}; 38