1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/interconnect/qcom,osm-l3.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Operating State Manager (OSM) L3 Interconnect Provider 8 9maintainers: 10 - Sibi Sankar <quic_sibis@quicinc.com> 11 12description: 13 L3 cache bandwidth requirements on Qualcomm SoCs is serviced by the OSM. 14 The OSM L3 interconnect provider aggregates the L3 bandwidth requests 15 from CPU/GPU and relays it to the OSM. 16 17properties: 18 compatible: 19 enum: 20 - qcom,sc7180-osm-l3 21 - qcom,sc7280-epss-l3 22 - qcom,sc8180x-osm-l3 23 - qcom,sdm845-osm-l3 24 - qcom,sm8150-osm-l3 25 - qcom,sm8250-epss-l3 26 27 reg: 28 maxItems: 1 29 30 clocks: 31 items: 32 - description: xo clock 33 - description: alternate clock 34 35 clock-names: 36 items: 37 - const: xo 38 - const: alternate 39 40 '#interconnect-cells': 41 const: 1 42 43required: 44 - compatible 45 - reg 46 - clocks 47 - clock-names 48 - '#interconnect-cells' 49 50additionalProperties: false 51 52examples: 53 - | 54 55 #define GPLL0 165 56 #define RPMH_CXO_CLK 0 57 58 osm_l3: interconnect@17d41000 { 59 compatible = "qcom,sdm845-osm-l3"; 60 reg = <0x17d41000 0x1400>; 61 62 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 63 clock-names = "xo", "alternate"; 64 65 #interconnect-cells = <1>; 66 }; 67