xref: /freebsd/sys/contrib/device-tree/Bindings/interconnect/qcom,osm-l3.yaml (revision 5ca8e32633c4ffbbcd6762e5888b6a4ba0708c6c) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interconnect/qcom,osm-l3.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Operating State Manager (OSM) L3 Interconnect Provider
8
9maintainers:
10  - Sibi Sankar <quic_sibis@quicinc.com>
11
12description:
13  L3 cache bandwidth requirements on Qualcomm SoCs is serviced by the OSM.
14  The OSM L3 interconnect provider aggregates the L3 bandwidth requests
15  from CPU/GPU and relays it to the OSM.
16
17properties:
18  compatible:
19    oneOf:
20      - items:
21          - enum:
22              - qcom,sc7180-osm-l3
23              - qcom,sc8180x-osm-l3
24              - qcom,sdm845-osm-l3
25              - qcom,sm6350-osm-l3
26              - qcom,sm8150-osm-l3
27          - const: qcom,osm-l3
28      - items:
29          - enum:
30              - qcom,sc7280-epss-l3
31              - qcom,sc8280xp-epss-l3
32              - qcom,sm6375-cpucp-l3
33              - qcom,sm8250-epss-l3
34              - qcom,sm8350-epss-l3
35          - const: qcom,epss-l3
36
37  reg:
38    maxItems: 1
39
40  clocks:
41    items:
42      - description: xo clock
43      - description: alternate clock
44
45  clock-names:
46    items:
47      - const: xo
48      - const: alternate
49
50  '#interconnect-cells':
51    const: 1
52
53required:
54  - compatible
55  - reg
56  - clocks
57  - clock-names
58  - '#interconnect-cells'
59
60additionalProperties: false
61
62examples:
63  - |
64
65    #define GPLL0               165
66    #define RPMH_CXO_CLK        0
67
68    osm_l3: interconnect@17d41000 {
69      compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3";
70      reg = <0x17d41000 0x1400>;
71
72      clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
73      clock-names = "xo", "alternate";
74
75      #interconnect-cells = <1>;
76    };
77