xref: /freebsd/sys/contrib/device-tree/Bindings/interconnect/mediatek,cci.yaml (revision b97ee269eae3cbaf35c18f51a459aea581c2a7dc) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interconnect/mediatek,cci.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek Cache Coherent Interconnect (CCI) frequency and voltage scaling
8
9maintainers:
10  - Jia-Wei Chang <jia-wei.chang@mediatek.com>
11  - Johnson Wang <johnson.wang@mediatek.com>
12
13description: |
14  MediaTek Cache Coherent Interconnect (CCI) is a hardware engine used by
15  MT8183 and MT8186 SoCs to scale the frequency and adjust the voltage in
16  hardware. It can also optimize the voltage to reduce the power consumption.
17
18properties:
19  compatible:
20    enum:
21      - mediatek,mt8183-cci
22      - mediatek,mt8186-cci
23
24  clocks:
25    items:
26      - description:
27          The multiplexer for clock input of the bus.
28      - description:
29          A parent of "bus" clock which is used as an intermediate clock source
30          when the original clock source (PLL) is under transition and not
31          stable yet.
32
33  clock-names:
34    items:
35      - const: cci
36      - const: intermediate
37
38  operating-points-v2: true
39  opp-table: true
40
41  proc-supply:
42    description:
43      Phandle of the regulator for CCI that provides the supply voltage.
44
45  sram-supply:
46    description:
47      Phandle of the regulator for sram of CCI that provides the supply
48      voltage. When it is present, the implementation needs to do
49      "voltage tracking" to step by step scale up/down Vproc and Vsram to fit
50      SoC specific needs. When absent, the voltage scaling flow is handled by
51      hardware, hence no software "voltage tracking" is needed.
52
53required:
54  - compatible
55  - clocks
56  - clock-names
57  - operating-points-v2
58  - proc-supply
59
60additionalProperties: false
61
62examples:
63  - |
64    #include <dt-bindings/clock/mt8183-clk.h>
65    cci: cci {
66        compatible = "mediatek,mt8183-cci";
67        clocks = <&mcucfg CLK_MCU_BUS_SEL>,
68                 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
69        clock-names = "cci", "intermediate";
70        operating-points-v2 = <&cci_opp>;
71        proc-supply = <&mt6358_vproc12_reg>;
72    };
73
74    cci_opp: opp-table-cci {
75        compatible = "operating-points-v2";
76        opp-shared;
77        opp2_00: opp-273000000 {
78            opp-hz = /bits/ 64 <273000000>;
79            opp-microvolt = <650000>;
80        };
81        opp2_01: opp-338000000 {
82            opp-hz = /bits/ 64 <338000000>;
83            opp-microvolt = <687500>;
84        };
85        opp2_02: opp-403000000 {
86            opp-hz = /bits/ 64 <403000000>;
87            opp-microvolt = <718750>;
88        };
89        opp2_03: opp-463000000 {
90            opp-hz = /bits/ 64 <463000000>;
91            opp-microvolt = <756250>;
92        };
93        opp2_04: opp-546000000 {
94            opp-hz = /bits/ 64 <546000000>;
95            opp-microvolt = <800000>;
96        };
97        opp2_05: opp-624000000 {
98            opp-hz = /bits/ 64 <624000000>;
99            opp-microvolt = <818750>;
100        };
101        opp2_06: opp-689000000 {
102            opp-hz = /bits/ 64 <689000000>;
103            opp-microvolt = <850000>;
104        };
105        opp2_07: opp-767000000 {
106            opp-hz = /bits/ 64 <767000000>;
107            opp-microvolt = <868750>;
108        };
109        opp2_08: opp-845000000 {
110            opp-hz = /bits/ 64 <845000000>;
111            opp-microvolt = <893750>;
112        };
113        opp2_09: opp-871000000 {
114            opp-hz = /bits/ 64 <871000000>;
115            opp-microvolt = <906250>;
116        };
117        opp2_10: opp-923000000 {
118            opp-hz = /bits/ 64 <923000000>;
119            opp-microvolt = <931250>;
120        };
121        opp2_11: opp-962000000 {
122            opp-hz = /bits/ 64 <962000000>;
123            opp-microvolt = <943750>;
124        };
125        opp2_12: opp-1027000000 {
126            opp-hz = /bits/ 64 <1027000000>;
127            opp-microvolt = <975000>;
128        };
129        opp2_13: opp-1092000000 {
130            opp-hz = /bits/ 64 <1092000000>;
131            opp-microvolt = <1000000>;
132        };
133        opp2_14: opp-1144000000 {
134            opp-hz = /bits/ 64 <1144000000>;
135            opp-microvolt = <1025000>;
136        };
137        opp2_15: opp-1196000000 {
138            opp-hz = /bits/ 64 <1196000000>;
139            opp-microvolt = <1050000>;
140        };
141    };
142