1 2Analog Devices ADIS16480 and similar IMUs 3 4Required properties for the ADIS16480: 5 6- compatible: Must be one of 7 * "adi,adis16375" 8 * "adi,adis16480" 9 * "adi,adis16485" 10 * "adi,adis16488" 11 * "adi,adis16490" 12 * "adi,adis16495-1" 13 * "adi,adis16495-2" 14 * "adi,adis16495-3" 15 * "adi,adis16497-1" 16 * "adi,adis16497-2" 17 * "adi,adis16497-3" 18- reg: SPI chip select number for the device 19- spi-max-frequency: Max SPI frequency to use 20 see: Documentation/devicetree/bindings/spi/spi-bus.txt 21- spi-cpha: See Documentation/devicetree/bindings/spi/spi-bus.txt 22- spi-cpol: See Documentation/devicetree/bindings/spi/spi-bus.txt 23- interrupts: interrupt mapping for IRQ, accepted values are: 24 * IRQF_TRIGGER_RISING 25 * IRQF_TRIGGER_FALLING 26 27Optional properties: 28 29- interrupt-names: Data ready line selection. Valid values are: 30 * DIO1 31 * DIO2 32 * DIO3 33 * DIO4 34 If this field is left empty, DIO1 is assigned as default data ready 35 signal. 36- reset-gpios: must be the device tree identifier of the RESET pin. As the line 37 is active low, it should be marked GPIO_ACTIVE_LOW. 38- clocks: phandle to the external clock. Should be set according to 39 "clock-names". 40 If this field is left empty together with the "clock-names" field, then 41 the internal clock is used. 42- clock-names: The name of the external clock to be used. Valid values are: 43 * sync: In sync mode, the internal clock is disabled and the frequency 44 of the external clock signal establishes therate of data 45 collection and processing. See Fig 14 and 15 in the datasheet. 46 The clock-frequency must be: 47 * 3000 to 4500 Hz for adis1649x devices. 48 * 700 to 2400 Hz for adis1648x devices. 49 * pps: In Pulse Per Second (PPS) Mode, the rate of data collection and 50 production is equal to the product of the external clock 51 frequency and the scale factor in the SYNC_SCALE register, see 52 Table 154 in the datasheet. 53 The clock-frequency must be: 54 * 1 to 128 Hz for adis1649x devices. 55 * This mode is not supported by adis1648x devices. 56 If this field is left empty together with the "clocks" field, then the 57 internal clock is used. 58- adi,ext-clk-pin: The DIOx line to be used as an external clock input. 59 Valid values are: 60 * DIO1 61 * DIO2 62 * DIO3 63 * DIO4 64 Each DIOx pin supports only one function at a time (data ready line 65 selection or external clock input). When a single pin has two 66 two assignments, the enable bit for the lower priority function 67 automatically resets to zero (disabling the lower priority function). 68 Data ready has highest priority. 69 If this field is left empty, DIO2 is assigned as default external clock 70 input pin. 71 72Example: 73 74 imu@0 { 75 compatible = "adi,adis16495-1"; 76 reg = <0>; 77 spi-max-frequency = <3200000>; 78 spi-cpol; 79 spi-cpha; 80 interrupts = <25 IRQF_TRIGGER_FALLING>; 81 interrupt-parent = <&gpio>; 82 interrupt-names = "DIO2"; 83 clocks = <&adis16495_sync>; 84 clock-names = "sync"; 85 adi,ext-clk-pin = "DIO1"; 86 }; 87