1Freescale vf610 Analog to Digital Converter bindings 2 3The devicetree bindings are for the new ADC driver written for 4vf610/i.MX6slx and upward SoCs from Freescale. 5 6Required properties: 7- compatible: Should contain "fsl,vf610-adc" 8- reg: Offset and length of the register set for the device 9- interrupts: Should contain the interrupt for the device 10- clocks: The clock is needed by the ADC controller, ADC clock source is ipg clock. 11- clock-names: Must contain "adc", matching entry in the clocks property. 12- vref-supply: The regulator supply ADC reference voltage. 13 14Recommended properties: 15- fsl,adck-max-frequency: Maximum frequencies according to datasheets operating 16 requirements. Three values are required, depending on conversion mode: 17 - Frequency in normal mode (ADLPC=0, ADHSC=0) 18 - Frequency in high-speed mode (ADLPC=0, ADHSC=1) 19 - Frequency in low-power mode (ADLPC=1, ADHSC=0) 20- min-sample-time: Minimum sampling time in nanoseconds. This value has 21 to be chosen according to the conversion mode and the connected analog 22 source resistance (R_as) and capacitance (C_as). Refer the datasheet's 23 operating requirements. A safe default across a wide range of R_as and 24 C_as as well as conversion modes is 1000ns. 25 26Example: 27adc0: adc@4003b000 { 28 compatible = "fsl,vf610-adc"; 29 reg = <0x4003b000 0x1000>; 30 interrupts = <0 53 0x04>; 31 clocks = <&clks VF610_CLK_ADC0>; 32 clock-names = "adc"; 33 fsl,adck-max-frequency = <30000000>, <40000000>, 34 <20000000>; 35 vref-supply = <®_vcc_3v3_mcu>; 36}; 37