1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/iio/adc/adi,axi-adc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Analog Devices AXI ADC IP core 8 9maintainers: 10 - Michael Hennerich <michael.hennerich@analog.com> 11 - Alexandru Ardelean <alexandru.ardelean@analog.com> 12 13description: | 14 Analog Devices Generic AXI ADC IP core for interfacing an ADC device 15 with a high speed serial (JESD204B/C) or source synchronous parallel 16 interface (LVDS/CMOS). 17 Usually, some other interface type (i.e SPI) is used as a control 18 interface for the actual ADC, while this IP core will interface 19 to the data-lines of the ADC and handle the streaming of data into 20 memory via DMA. 21 22 https://wiki.analog.com/resources/fpga/docs/axi_adc_ip 23 24properties: 25 compatible: 26 enum: 27 - adi,axi-adc-10.0.a 28 29 reg: 30 maxItems: 1 31 32 dmas: 33 maxItems: 1 34 35 dma-names: 36 items: 37 - const: rx 38 39 adi,adc-dev: 40 $ref: /schemas/types.yaml#/definitions/phandle 41 description: 42 A reference to a the actual ADC to which this FPGA ADC interfaces to. 43 44required: 45 - compatible 46 - dmas 47 - reg 48 - adi,adc-dev 49 50additionalProperties: false 51 52examples: 53 - | 54 axi-adc@44a00000 { 55 compatible = "adi,axi-adc-10.0.a"; 56 reg = <0x44a00000 0x10000>; 57 dmas = <&rx_dma 0>; 58 dma-names = "rx"; 59 60 adi,adc-dev = <&spi_adc>; 61 }; 62... 63