1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/i2c/renesas,rcar-i2c.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Renesas R-Car I2C Controller 8 9maintainers: 10 - Wolfram Sang <wsa+renesas@sang-engineering.com> 11 12properties: 13 compatible: 14 oneOf: 15 - items: 16 - enum: 17 - renesas,i2c-r8a7778 # R-Car M1A 18 - renesas,i2c-r8a7779 # R-Car H1 19 - const: renesas,rcar-gen1-i2c # R-Car Gen1 20 21 - items: 22 - enum: 23 - renesas,i2c-r8a7742 # RZ/G1H 24 - renesas,i2c-r8a7743 # RZ/G1M 25 - renesas,i2c-r8a7744 # RZ/G1N 26 - renesas,i2c-r8a7745 # RZ/G1E 27 - renesas,i2c-r8a77470 # RZ/G1C 28 - renesas,i2c-r8a7790 # R-Car H2 29 - renesas,i2c-r8a7791 # R-Car M2-W 30 - renesas,i2c-r8a7792 # R-Car V2H 31 - renesas,i2c-r8a7793 # R-Car M2-N 32 - renesas,i2c-r8a7794 # R-Car E2 33 - const: renesas,rcar-gen2-i2c # R-Car Gen2 and RZ/G1 34 35 - items: 36 - enum: 37 - renesas,i2c-r8a774a1 # RZ/G2M 38 - renesas,i2c-r8a774b1 # RZ/G2N 39 - renesas,i2c-r8a774c0 # RZ/G2E 40 - renesas,i2c-r8a774e1 # RZ/G2H 41 - renesas,i2c-r8a7795 # R-Car H3 42 - renesas,i2c-r8a7796 # R-Car M3-W 43 - renesas,i2c-r8a77961 # R-Car M3-W+ 44 - renesas,i2c-r8a77965 # R-Car M3-N 45 - renesas,i2c-r8a77970 # R-Car V3M 46 - renesas,i2c-r8a77980 # R-Car V3H 47 - renesas,i2c-r8a77990 # R-Car E3 48 - renesas,i2c-r8a77995 # R-Car D3 49 - const: renesas,rcar-gen3-i2c # R-Car Gen3 and RZ/G2 50 51 - items: 52 - enum: 53 - renesas,i2c-r8a779a0 # R-Car V3U 54 - renesas,i2c-r8a779f0 # R-Car S4-8 55 - const: renesas,rcar-gen4-i2c # R-Car Gen4 56 57 reg: 58 maxItems: 1 59 60 interrupts: 61 maxItems: 1 62 63 clock-frequency: 64 description: 65 Desired I2C bus clock frequency in Hz. The absence of this property 66 indicates the default frequency 100 kHz. 67 68 clocks: 69 maxItems: 1 70 71 power-domains: 72 maxItems: 1 73 74 resets: 75 maxItems: 1 76 77 dmas: 78 minItems: 2 79 maxItems: 4 80 description: 81 Must contain a list of pairs of references to DMA specifiers, one for 82 transmission, and one for reception. 83 84 dma-names: 85 minItems: 2 86 maxItems: 4 87 items: 88 enum: 89 - tx 90 - rx 91 92 i2c-scl-falling-time-ns: 93 default: 35 94 description: 95 Number of nanoseconds the SCL signal takes to fall; t(f) in the I2C 96 specification. 97 98 i2c-scl-internal-delay-ns: 99 default: 50 100 description: 101 Number of nanoseconds the IP core additionally needs to setup SCL. 102 103 i2c-scl-rising-time-ns: 104 default: 200 105 description: 106 Number of nanoseconds the SCL signal takes to rise; t(r) in the I2C 107 specification. 108 109required: 110 - compatible 111 - reg 112 - interrupts 113 - clocks 114 - power-domains 115 - '#address-cells' 116 - '#size-cells' 117 118allOf: 119 - $ref: /schemas/i2c/i2c-controller.yaml# 120 121 - if: 122 properties: 123 compatible: 124 contains: 125 enum: 126 - renesas,rcar-gen1-i2c 127 - renesas,rcar-gen2-i2c 128 then: 129 properties: 130 dmas: false 131 dma-names: false 132 133 - if: 134 properties: 135 compatible: 136 contains: 137 enum: 138 - renesas,rcar-gen2-i2c 139 - renesas,rcar-gen3-i2c 140 - renesas,rcar-gen4-i2c 141 then: 142 required: 143 - resets 144 145unevaluatedProperties: false 146 147examples: 148 - | 149 #include <dt-bindings/clock/r8a7791-cpg-mssr.h> 150 #include <dt-bindings/interrupt-controller/arm-gic.h> 151 #include <dt-bindings/power/r8a7791-sysc.h> 152 153 i2c0: i2c@e6508000 { 154 #address-cells = <1>; 155 #size-cells = <0>; 156 compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; 157 reg = <0xe6508000 0x40>; 158 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 159 clock-frequency = <400000>; 160 clocks = <&cpg CPG_MOD 931>; 161 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 162 resets = <&cpg 931>; 163 i2c-scl-internal-delay-ns = <6>; 164 }; 165