1NVIDIA Tegra20/Tegra30/Tegra114 I2C controller driver. 2 3Required properties: 4- compatible : For Tegra20, must be one of "nvidia,tegra20-i2c-dvc" or 5 "nvidia,tegra20-i2c". For Tegra30, must be "nvidia,tegra30-i2c". 6 For Tegra114, must be "nvidia,tegra114-i2c". Otherwise, must be 7 "nvidia,<chip>-i2c", plus at least one of the above, where <chip> is 8 tegra124, tegra132, or tegra210. 9 Details of compatible are as follows: 10 nvidia,tegra20-i2c-dvc: Tegra20 has specific I2C controller called as DVC I2C 11 controller. This only support master mode of I2C communication. Register 12 interface/offset and interrupts handling are different than generic I2C 13 controller. Driver of DVC I2C controller is only compatible with 14 "nvidia,tegra20-i2c-dvc". 15 nvidia,tegra20-i2c: Tegra20 has 4 generic I2C controller. This can support 16 master and slave mode of I2C communication. The i2c-tegra driver only 17 support master mode of I2C communication. Driver of I2C controller is 18 only compatible with "nvidia,tegra20-i2c". 19 nvidia,tegra30-i2c: Tegra30 has 5 generic I2C controller. This controller is 20 very much similar to Tegra20 I2C controller with additional feature: 21 Continue Transfer Support. This feature helps to implement M_NO_START 22 as per I2C core API transfer flags. Driver of I2C controller is 23 compatible with "nvidia,tegra30-i2c" to enable the continue transfer 24 support. This is also compatible with "nvidia,tegra20-i2c" without 25 continue transfer support. 26 nvidia,tegra114-i2c: Tegra114 has 5 generic I2C controller. This controller is 27 very much similar to Tegra30 I2C controller with some hardware 28 modification: 29 - Tegra30/Tegra20 I2C controller has 2 clock source called div-clk and 30 fast-clk. Tegra114 has only one clock source called as div-clk and 31 hence clock mechanism is changed in I2C controller. 32 - Tegra30/Tegra20 I2C controller has enabled per packet transfer by 33 default and there is no way to disable it. Tegra114 has this 34 interrupt disable by default and SW need to enable explicitly. 35 Due to above changes, Tegra114 I2C driver makes incompatible with 36 previous hardware driver. Hence, tegra114 I2C controller is compatible 37 with "nvidia,tegra114-i2c". 38 nvidia,tegra210-i2c-vi: Tegra210 has one I2C controller that is on host1x bus 39 and is part of VE power domain and typically used for camera use-cases. 40 This VI I2C controller is mostly compatible with the programming model 41 of the regular I2C controllers with a few exceptions. The I2C registers 42 start at an offset of 0xc00 (instead of 0), registers are 16 bytes 43 apart (rather than 4) and the controller does not support slave mode. 44- reg: Should contain I2C controller registers physical address and length. 45- interrupts: Should contain I2C controller interrupts. 46- address-cells: Address cells for I2C device address. 47- size-cells: Size of the I2C device address. 48- clocks: Must contain an entry for each entry in clock-names. 49 See ../clocks/clock-bindings.txt for details. 50- clock-names: Must include the following entries: 51 Tegra20/Tegra30: 52 - div-clk 53 - fast-clk 54 Tegra114: 55 - div-clk 56 Tegra210: 57 - div-clk 58 - slow (only for nvidia,tegra210-i2c-vi compatible node) 59- resets: Must contain an entry for each entry in reset-names. 60 See ../reset/reset.txt for details. 61- reset-names: Must include the following entries: 62 - i2c 63- power-domains: Only for nvidia,tegra210-i2c-vi compatible node and must 64 include venc powergate node as vi i2c is part of VE power domain. 65 tegra210-i2c-vi: 66 - pd_venc 67- dmas: Must contain an entry for each entry in clock-names. 68 See ../dma/dma.txt for details. 69- dma-names: Must include the following entries: 70 - rx 71 - tx 72 73Example: 74 75 i2c@7000c000 { 76 compatible = "nvidia,tegra20-i2c"; 77 reg = <0x7000c000 0x100>; 78 interrupts = <0 38 0x04>; 79 #address-cells = <1>; 80 #size-cells = <0>; 81 clocks = <&tegra_car 12>, <&tegra_car 124>; 82 clock-names = "div-clk", "fast-clk"; 83 resets = <&tegra_car 12>; 84 reset-names = "i2c"; 85 dmas = <&apbdma 16>, <&apbdma 16>; 86 dma-names = "rx", "tx"; 87 }; 88