xref: /freebsd/sys/contrib/device-tree/Bindings/i2c/mellanox,i2c-mlxbf.yaml (revision 5def4c47d4bd90b209b9b4a4ba9faec15846d8fd) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/i2c/mellanox,i2c-mlxbf.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mellanox I2C SMBus on BlueField SoCs
8
9maintainers:
10  - Khalil Blaiech <kblaiech@nvidia.com>
11
12allOf:
13  - $ref: /schemas/i2c/i2c-controller.yaml#
14
15properties:
16  compatible:
17    enum:
18      - mellanox,i2c-mlxbf1
19      - mellanox,i2c-mlxbf2
20
21  reg:
22    minItems: 3
23    maxItems: 4
24    items:
25      - description: Smbus block registers
26      - description: Cause master registers
27      - description: Cause slave registers
28      - description: Cause coalesce registers
29
30  interrupts:
31    maxItems: 1
32
33  clock-frequency:
34    enum: [ 100000, 400000, 1000000 ]
35    description:
36      bus frequency used to configure timing registers;
37      The frequency is expressed in Hz. Default is 100000.
38
39required:
40  - compatible
41  - reg
42  - interrupts
43
44unevaluatedProperties: false
45
46if:
47  properties:
48    compatible:
49      contains:
50        enum:
51          - mellanox,i2c-mlxbf1
52
53then:
54  properties:
55    reg:
56      maxItems: 3
57
58examples:
59  - |
60    i2c@2804000 {
61        compatible = "mellanox,i2c-mlxbf1";
62        reg = <0x02804000 0x800>,
63              <0x02801200 0x020>,
64              <0x02801260 0x020>;
65        interrupts = <57>;
66        clock-frequency = <100000>;
67    };
68
69  - |
70    i2c@2808800 {
71        compatible = "mellanox,i2c-mlxbf2";
72        reg = <0x02808800 0x600>,
73              <0x02808e00 0x020>,
74              <0x02808e20 0x020>,
75              <0x02808e40 0x010>;
76        interrupts = <57>;
77        clock-frequency = <400000>;
78    };
79