1Device tree configuration for i2c-ocores 2 3Required properties: 4- compatible : "opencores,i2c-ocores" 5 "aeroflexgaisler,i2cmst" 6 "sifive,fu540-c000-i2c", "sifive,i2c0" 7 For Opencore based I2C IP block reimplemented in 8 FU540-C000 SoC. 9 "sifive,fu740-c000-i2c", "sifive,i2c0" 10 For Opencore based I2C IP block reimplemented in 11 FU740-C000 SoC. 12 Please refer to sifive-blocks-ip-versioning.txt for 13 additional details. 14- reg : bus address start and address range size of device 15- clocks : handle to the controller clock; see the note below. 16 Mutually exclusive with opencores,ip-clock-frequency 17- opencores,ip-clock-frequency: frequency of the controller clock in Hz; 18 see the note below. Mutually exclusive with clocks 19- #address-cells : should be <1> 20- #size-cells : should be <0> 21 22Optional properties: 23- interrupts : interrupt number. 24- clock-frequency : frequency of bus clock in Hz; see the note below. 25 Defaults to 100 KHz when the property is not specified 26- reg-shift : device register offsets are shifted by this value 27- reg-io-width : io register width in bytes (1, 2 or 4) 28- regstep : deprecated, use reg-shift above 29 30Note 31clock-frequency property is meant to control the bus frequency for i2c bus 32drivers, but it was incorrectly used to specify i2c controller input clock 33frequency. So the following rules are set to fix this situation: 34- if clock-frequency is present and neither opencores,ip-clock-frequency nor 35 clocks are, then clock-frequency specifies i2c controller clock frequency. 36 This is to keep backwards compatibility with setups using old DTB. i2c bus 37 frequency is fixed at 100 KHz. 38- if clocks is present it specifies i2c controller clock. clock-frequency 39 property specifies i2c bus frequency. 40- if opencores,ip-clock-frequency is present it specifies i2c controller 41 clock frequency. clock-frequency property specifies i2c bus frequency. 42 43Examples: 44 45 i2c0: ocores@a0000000 { 46 #address-cells = <1>; 47 #size-cells = <0>; 48 compatible = "opencores,i2c-ocores"; 49 reg = <0xa0000000 0x8>; 50 interrupts = <10>; 51 opencores,ip-clock-frequency = <20000000>; 52 53 reg-shift = <0>; /* 8 bit registers */ 54 reg-io-width = <1>; /* 8 bit read/write */ 55 56 dummy@60 { 57 compatible = "dummy"; 58 reg = <0x60>; 59 }; 60 }; 61or 62 i2c0: ocores@a0000000 { 63 #address-cells = <1>; 64 #size-cells = <0>; 65 compatible = "opencores,i2c-ocores"; 66 reg = <0xa0000000 0x8>; 67 interrupts = <10>; 68 clocks = <&osc>; 69 clock-frequency = <400000>; /* i2c bus frequency 400 KHz */ 70 71 reg-shift = <0>; /* 8 bit registers */ 72 reg-io-width = <1>; /* 8 bit read/write */ 73 74 dummy@60 { 75 compatible = "dummy"; 76 reg = <0x60>; 77 }; 78 }; 79