1# SPDX-License-Identifier: GPL-2.0-only 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/gpu/arm,mali-utgard.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM Mali Utgard GPU 8 9maintainers: 10 - Rob Herring <robh@kernel.org> 11 - Maxime Ripard <maxime.ripard@free-electrons.com> 12 - Heiko Stuebner <heiko@sntech.de> 13 14properties: 15 $nodename: 16 pattern: '^gpu@[a-f0-9]+$' 17 compatible: 18 oneOf: 19 - items: 20 - const: allwinner,sun8i-a23-mali 21 - const: allwinner,sun7i-a20-mali 22 - const: arm,mali-400 23 - items: 24 - enum: 25 - allwinner,sun4i-a10-mali 26 - allwinner,sun7i-a20-mali 27 - allwinner,sun8i-h3-mali 28 - allwinner,sun50i-a64-mali 29 - rockchip,rk3036-mali 30 - rockchip,rk3066-mali 31 - rockchip,rk3188-mali 32 - rockchip,rk3228-mali 33 - samsung,exynos4210-mali 34 - stericsson,db8500-mali 35 - const: arm,mali-400 36 - items: 37 - enum: 38 - allwinner,sun50i-h5-mali 39 - amlogic,meson8-mali 40 - amlogic,meson8b-mali 41 - amlogic,meson-gxbb-mali 42 - amlogic,meson-gxl-mali 43 - hisilicon,hi6220-mali 44 - mediatek,mt7623-mali 45 - rockchip,rk3328-mali 46 - const: arm,mali-450 47 48 # "arm,mali-300" 49 50 reg: 51 maxItems: 1 52 53 interrupts: 54 minItems: 4 55 maxItems: 20 56 57 interrupt-names: 58 allOf: 59 - additionalItems: true 60 minItems: 4 61 maxItems: 20 62 items: 63 # At least enforce the first 2 interrupts 64 - const: gp 65 - const: gpmmu 66 - items: 67 # Not ideal as any order and combination are allowed 68 enum: 69 - gp # Geometry Processor interrupt 70 - gpmmu # Geometry Processor MMU interrupt 71 - pp # Pixel Processor broadcast interrupt (mali-450 only) 72 - pp0 # Pixel Processor X interrupt (X from 0 to 7) 73 - ppmmu0 # Pixel Processor X MMU interrupt (X from 0 to 7) 74 - pp1 75 - ppmmu1 76 - pp2 77 - ppmmu2 78 - pp3 79 - ppmmu3 80 - pp4 81 - ppmmu4 82 - pp5 83 - ppmmu5 84 - pp6 85 - ppmmu6 86 - pp7 87 - ppmmu7 88 - pmu # Power Management Unit interrupt (optional) 89 - combined # stericsson,db8500-mali only 90 91 clocks: 92 maxItems: 2 93 94 clock-names: 95 items: 96 - const: bus 97 - const: core 98 99 memory-region: true 100 101 mali-supply: true 102 103 power-domains: 104 maxItems: 1 105 106 resets: 107 maxItems: 1 108 109 operating-points-v2: true 110 111 "#cooling-cells": 112 const: 2 113 114required: 115 - compatible 116 - reg 117 - interrupts 118 - interrupt-names 119 - clocks 120 - clock-names 121 122additionalProperties: false 123 124allOf: 125 - if: 126 properties: 127 compatible: 128 contains: 129 enum: 130 - allwinner,sun4i-a10-mali 131 - allwinner,sun7i-a20-mali 132 - allwinner,sun50i-a64-mali 133 - allwinner,sun50i-h5-mali 134 - amlogic,meson8-mali 135 - amlogic,meson8b-mali 136 - hisilicon,hi6220-mali 137 - mediatek,mt7623-mali 138 - rockchip,rk3036-mali 139 - rockchip,rk3066-mali 140 - rockchip,rk3188-mali 141 - rockchip,rk3228-mali 142 - rockchip,rk3328-mali 143 then: 144 required: 145 - resets 146 147examples: 148 - | 149 #include <dt-bindings/interrupt-controller/irq.h> 150 #include <dt-bindings/interrupt-controller/arm-gic.h> 151 152 mali: gpu@1c40000 { 153 compatible = "allwinner,sun7i-a20-mali", "arm,mali-400"; 154 reg = <0x01c40000 0x10000>; 155 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 162 interrupt-names = "gp", 163 "gpmmu", 164 "pp0", 165 "ppmmu0", 166 "pp1", 167 "ppmmu1", 168 "pmu"; 169 clocks = <&ccu 1>, <&ccu 2>; 170 clock-names = "bus", "core"; 171 resets = <&ccu 1>; 172 #cooling-cells = <2>; 173 }; 174 175... 176