1# SPDX-License-Identifier: GPL-2.0-only 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/gpu/arm,mali-utgard.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM Mali Utgard GPU 8 9maintainers: 10 - Rob Herring <robh@kernel.org> 11 - Maxime Ripard <mripard@kernel.org> 12 - Heiko Stuebner <heiko@sntech.de> 13 14properties: 15 $nodename: 16 pattern: '^gpu@[a-f0-9]+$' 17 compatible: 18 oneOf: 19 - items: 20 - const: allwinner,sun8i-a23-mali 21 - const: allwinner,sun7i-a20-mali 22 - const: arm,mali-400 23 - items: 24 - enum: 25 - allwinner,sun4i-a10-mali 26 - allwinner,sun7i-a20-mali 27 - allwinner,sun8i-h3-mali 28 - allwinner,sun8i-r40-mali 29 - allwinner,sun50i-a64-mali 30 - rockchip,rk3036-mali 31 - rockchip,rk3066-mali 32 - rockchip,rk3188-mali 33 - rockchip,rk3228-mali 34 - samsung,exynos4210-mali 35 - stericsson,db8500-mali 36 - const: arm,mali-400 37 - items: 38 - enum: 39 - allwinner,sun50i-h5-mali 40 - amlogic,meson8-mali 41 - amlogic,meson8b-mali 42 - amlogic,meson-gxbb-mali 43 - amlogic,meson-gxl-mali 44 - hisilicon,hi6220-mali 45 - mediatek,mt7623-mali 46 - rockchip,rk3328-mali 47 - const: arm,mali-450 48 49 # "arm,mali-300" 50 51 reg: 52 maxItems: 1 53 54 interrupts: 55 minItems: 4 56 maxItems: 20 57 58 interrupt-names: 59 allOf: 60 - additionalItems: true 61 minItems: 4 62 maxItems: 20 63 items: 64 # At least enforce the first 2 interrupts 65 - const: gp 66 - const: gpmmu 67 - items: 68 # Not ideal as any order and combination are allowed 69 enum: 70 - gp # Geometry Processor interrupt 71 - gpmmu # Geometry Processor MMU interrupt 72 - pp # Pixel Processor broadcast interrupt (mali-450 only) 73 - pp0 # Pixel Processor X interrupt (X from 0 to 7) 74 - ppmmu0 # Pixel Processor X MMU interrupt (X from 0 to 7) 75 - pp1 76 - ppmmu1 77 - pp2 78 - ppmmu2 79 - pp3 80 - ppmmu3 81 - pp4 82 - ppmmu4 83 - pp5 84 - ppmmu5 85 - pp6 86 - ppmmu6 87 - pp7 88 - ppmmu7 89 - pmu # Power Management Unit interrupt (optional) 90 - combined # stericsson,db8500-mali only 91 92 clocks: 93 maxItems: 2 94 95 clock-names: 96 items: 97 - const: bus 98 - const: core 99 100 memory-region: true 101 102 mali-supply: true 103 104 opp-table: 105 type: object 106 107 power-domains: 108 maxItems: 1 109 110 resets: 111 maxItems: 1 112 113 operating-points-v2: true 114 115 "#cooling-cells": 116 const: 2 117 118required: 119 - compatible 120 - reg 121 - interrupts 122 - interrupt-names 123 - clocks 124 - clock-names 125 126additionalProperties: false 127 128allOf: 129 - if: 130 properties: 131 compatible: 132 contains: 133 enum: 134 - allwinner,sun4i-a10-mali 135 - allwinner,sun7i-a20-mali 136 - allwinner,sun8i-r40-mali 137 - allwinner,sun50i-a64-mali 138 - allwinner,sun50i-h5-mali 139 - amlogic,meson8-mali 140 - amlogic,meson8b-mali 141 - hisilicon,hi6220-mali 142 - mediatek,mt7623-mali 143 - rockchip,rk3036-mali 144 - rockchip,rk3066-mali 145 - rockchip,rk3188-mali 146 - rockchip,rk3228-mali 147 - rockchip,rk3328-mali 148 then: 149 required: 150 - resets 151 152examples: 153 - | 154 #include <dt-bindings/interrupt-controller/irq.h> 155 #include <dt-bindings/interrupt-controller/arm-gic.h> 156 157 mali: gpu@1c40000 { 158 compatible = "allwinner,sun7i-a20-mali", "arm,mali-400"; 159 reg = <0x01c40000 0x10000>; 160 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 167 interrupt-names = "gp", 168 "gpmmu", 169 "pp0", 170 "ppmmu0", 171 "pp1", 172 "ppmmu1", 173 "pmu"; 174 clocks = <&ccu 1>, <&ccu 2>; 175 clock-names = "bus", "core"; 176 resets = <&ccu 1>; 177 #cooling-cells = <2>; 178 }; 179 180... 181