1=== ST Microelectronics SPEAr SPI CS Driver === 2 3SPEAr platform provides a provision to control chipselects of ARM PL022 Prime 4Cell spi controller through its system registers, which otherwise remains under 5PL022 control. If chipselect remain under PL022 control then they would be 6released as soon as transfer is over and TxFIFO becomes empty. This is not 7desired by some of the device protocols above spi which expect (multiple) 8transfers without releasing their chipselects. 9 10Chipselects can be controlled by software by turning them as GPIOs. SPEAr 11provides another interface through system registers through which software can 12directly control each PL022 chipselect. Hence, it is natural for SPEAr to export 13the control of this interface as gpio. 14 15Required properties: 16 17 * compatible: should be defined as "st,spear-spics-gpio" 18 * reg: mentioning address range of spics controller 19 * st-spics,peripcfg-reg: peripheral configuration register offset 20 * st-spics,sw-enable-bit: bit offset to enable sw control 21 * st-spics,cs-value-bit: bit offset to drive chipselect low or high 22 * st-spics,cs-enable-mask: chip select number bit mask 23 * st-spics,cs-enable-shift: chip select number program offset 24 * gpio-controller: Marks the device node as gpio controller 25 * #gpio-cells: should be 1 and will mention chip select number 26 27All the above bit offsets are within peripcfg register. 28 29Example: 30------- 31spics: spics@e0700000{ 32 compatible = "st,spear-spics-gpio"; 33 reg = <0xe0700000 0x1000>; 34 st-spics,peripcfg-reg = <0x3b0>; 35 st-spics,sw-enable-bit = <12>; 36 st-spics,cs-value-bit = <11>; 37 st-spics,cs-enable-mask = <3>; 38 st-spics,cs-enable-shift = <8>; 39 gpio-controller; 40 #gpio-cells = <2>; 41}; 42 43 44spi0: spi@e0100000 { 45 num-cs = <3>; 46 cs-gpios = <&gpio1 7 0>, <&spics 0>, 47 <&spics 1>; 48 ... 49} 50