xref: /freebsd/sys/contrib/device-tree/Bindings/gpio/rockchip,gpio-bank.yaml (revision e6bfd18d21b225af6a0ed67ceeaf1293b7b9eba5) 
1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/gpio/rockchip,gpio-bank.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip GPIO bank
8
9maintainers:
10  - Heiko Stuebner <heiko@sntech.de>
11
12properties:
13  compatible:
14    enum:
15      - rockchip,gpio-bank
16      - rockchip,rk3188-gpio-bank0
17
18  reg:
19    maxItems: 1
20
21  interrupts:
22    maxItems: 1
23
24  clocks:
25    minItems: 1
26    items:
27      - description: APB interface clock source
28      - description: GPIO debounce reference clock source
29
30  gpio-ranges: true
31
32  gpio-controller: true
33
34  gpio-line-names: true
35
36  "#gpio-cells":
37    const: 2
38
39  interrupt-controller: true
40
41  "#interrupt-cells":
42    const: 2
43
44required:
45  - compatible
46  - reg
47  - interrupts
48  - clocks
49  - gpio-controller
50  - "#gpio-cells"
51  - interrupt-controller
52  - "#interrupt-cells"
53
54additionalProperties: false
55
56examples:
57  - |
58    #include <dt-bindings/interrupt-controller/arm-gic.h>
59    pinctrl: pinctrl {
60      #address-cells = <1>;
61      #size-cells = <1>;
62      ranges;
63
64      gpio0: gpio@2000a000 {
65        compatible = "rockchip,rk3188-gpio-bank0";
66        reg = <0x2000a000 0x100>;
67        interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
68        clocks = <&clk_gates8 9>;
69
70        gpio-controller;
71        #gpio-cells = <2>;
72
73        interrupt-controller;
74        #interrupt-cells = <2>;
75      };
76
77      gpio1: gpio@2003c000 {
78        compatible = "rockchip,gpio-bank";
79        reg = <0x2003c000 0x100>;
80        interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
81        clocks = <&clk_gates8 10>;
82
83        gpio-controller;
84        #gpio-cells = <2>;
85
86        interrupt-controller;
87        #interrupt-cells = <2>;
88      };
89    };
90