1NVIDIA Tegra186 GPIO controllers 2 3Tegra186 contains two GPIO controllers; a main controller and an "AON" 4controller. This binding document applies to both controllers. The register 5layouts for the controllers share many similarities, but also some significant 6differences. Hence, this document describes closely related but different 7bindings and compatible values. 8 9The Tegra186 GPIO controller allows software to set the IO direction of, and 10read/write the value of, numerous GPIO signals. Routing of GPIO signals to 11package balls is under the control of a separate pin controller HW block. Two 12major sets of registers exist: 13 14a) Security registers, which allow configuration of allowed access to the GPIO 15register set. These registers exist in a single contiguous block of physical 16address space. The size of this block, and the security features available, 17varies between the different GPIO controllers. 18 19Access to this set of registers is not necessary in all circumstances. Code 20that wishes to configure access to the GPIO registers needs access to these 21registers to do so. Code which simply wishes to read or write GPIO data does not 22need access to these registers. 23 24b) GPIO registers, which allow manipulation of the GPIO signals. In some GPIO 25controllers, these registers are exposed via multiple "physical aliases" in 26address space, each of which access the same underlying state. See the hardware 27documentation for rationale. Any particular GPIO client is expected to access 28just one of these physical aliases. 29 30Tegra HW documentation describes a unified naming convention for all GPIOs 31implemented by the SoC. Each GPIO is assigned to a port, and a port may control 32a number of GPIOs. Thus, each GPIO is named according to an alphabetical port 33name and an integer GPIO name within the port. For example, GPIO_PA0, GPIO_PN6, 34or GPIO_PCC3. 35 36The number of ports implemented by each GPIO controller varies. The number of 37implemented GPIOs within each port varies. GPIO registers within a controller 38are grouped and laid out according to the port they affect. 39 40The mapping from port name to the GPIO controller that implements that port, and 41the mapping from port name to register offset within a controller, are both 42extremely non-linear. The header file <dt-bindings/gpio/tegra186-gpio.h> 43describes the port-level mapping. In that file, the naming convention for ports 44matches the HW documentation. The values chosen for the names are alphabetically 45sorted within a particular controller. Drivers need to map between the DT GPIO 46IDs and HW register offsets using a lookup table. 47 48Each GPIO controller can generate a number of interrupt signals. Each signal 49represents the aggregate status for all GPIOs within a set of ports. Thus, the 50number of interrupt signals generated by a controller varies as a rough function 51of the number of ports it implements. Note that the HW documentation refers to 52both the overall controller HW module and the sets-of-ports as "controllers". 53 54Each GPIO controller in fact generates multiple interrupts signals for each set 55of ports. Each GPIO may be configured to feed into a specific one of the 56interrupt signals generated by a set-of-ports. The intent is for each generated 57signal to be routed to a different CPU, thus allowing different CPUs to each 58handle subsets of the interrupts within a port. The status of each of these 59per-port-set signals is reported via a separate register. Thus, a driver needs 60to know which status register to observe. This binding currently defines no 61configuration mechanism for this. By default, drivers should use register 62GPIO_${port}_INTERRUPT_STATUS_G1_0. Future revisions to the binding could 63define a property to configure this. 64 65Required properties: 66- compatible 67 Array of strings. 68 One of: 69 - "nvidia,tegra186-gpio". 70 - "nvidia,tegra186-gpio-aon". 71 - "nvidia,tegra194-gpio". 72 - "nvidia,tegra194-gpio-aon". 73- reg-names 74 Array of strings. 75 Contains a list of names for the register spaces described by the reg 76 property. May contain the following entries, in any order: 77 - "gpio": Mandatory. GPIO control registers. This may cover either: 78 a) The single physical alias that this OS should use. 79 b) All physical aliases that exist in the controller. This is 80 appropriate when the OS is responsible for managing assignment of 81 the physical aliases. 82 - "security": Optional. Security configuration registers. 83 Users of this binding MUST look up entries in the reg property by name, 84 using this reg-names property to do so. 85- reg 86 Array of (physical base address, length) tuples. 87 Must contain one entry per entry in the reg-names property, in a matching 88 order. 89- interrupts 90 Array of interrupt specifiers. 91 The interrupt outputs from the HW block, one per set of ports, in the 92 order the HW manual describes them. The number of entries required varies 93 depending on compatible value: 94 - "nvidia,tegra186-gpio": 6 entries. 95 - "nvidia,tegra186-gpio-aon": 1 entry. 96 - "nvidia,tegra194-gpio": 6 entries. 97 - "nvidia,tegra194-gpio-aon": 1 entry. 98- gpio-controller 99 Boolean. 100 Marks the device node as a GPIO controller/provider. 101- #gpio-cells 102 Single-cell integer. 103 Must be <2>. 104 Indicates how many cells are used in a consumer's GPIO specifier. 105 In the specifier: 106 - The first cell is the pin number. 107 See <dt-bindings/gpio/tegra186-gpio.h>. 108 - The second cell contains flags: 109 - Bit 0 specifies polarity 110 - 0: Active-high (normal). 111 - 1: Active-low (inverted). 112- interrupt-controller 113 Boolean. 114 Marks the device node as an interrupt controller/provider. 115- #interrupt-cells 116 Single-cell integer. 117 Must be <2>. 118 Indicates how many cells are used in a consumer's interrupt specifier. 119 In the specifier: 120 - The first cell is the GPIO number. 121 See <dt-bindings/gpio/tegra186-gpio.h>. 122 - The second cell is contains flags: 123 - Bits [3:0] indicate trigger type and level: 124 - 1: Low-to-high edge triggered. 125 - 2: High-to-low edge triggered. 126 - 4: Active high level-sensitive. 127 - 8: Active low level-sensitive. 128 Valid combinations are 1, 2, 3, 4, 8. 129 130Example: 131 132#include <dt-bindings/interrupt-controller/irq.h> 133 134gpio@2200000 { 135 compatible = "nvidia,tegra186-gpio"; 136 reg-names = "security", "gpio"; 137 reg = 138 <0x0 0x2200000 0x0 0x10000>, 139 <0x0 0x2210000 0x0 0x10000>; 140 interrupts = 141 <0 47 IRQ_TYPE_LEVEL_HIGH>, 142 <0 50 IRQ_TYPE_LEVEL_HIGH>, 143 <0 53 IRQ_TYPE_LEVEL_HIGH>, 144 <0 56 IRQ_TYPE_LEVEL_HIGH>, 145 <0 59 IRQ_TYPE_LEVEL_HIGH>, 146 <0 180 IRQ_TYPE_LEVEL_HIGH>; 147 gpio-controller; 148 #gpio-cells = <2>; 149 interrupt-controller; 150 #interrupt-cells = <2>; 151}; 152 153gpio@c2f0000 { 154 compatible = "nvidia,tegra186-gpio-aon"; 155 reg-names = "security", "gpio"; 156 reg = 157 <0x0 0xc2f0000 0x0 0x1000>, 158 <0x0 0xc2f1000 0x0 0x1000>; 159 interrupts = 160 <0 60 IRQ_TYPE_LEVEL_HIGH>; 161 gpio-controller; 162 #gpio-cells = <2>; 163 interrupt-controller; 164 #interrupt-cells = <2>; 165}; 166