1* Marvell EBU GPIO controller 2 3Required properties: 4 5- compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio", 6 "marvell,armadaxp-gpio" or "marvell,armada-8k-gpio". 7 8 "marvell,orion-gpio" should be used for Orion, Kirkwood, Dove, 9 Discovery (except MV78200) and Armada 370. "marvell,mv78200-gpio" 10 should be used for the Discovery MV78200. 11 12 "marvel,armadaxp-gpio" should be used for all Armada XP SoCs 13 (MV78230, MV78260, MV78460). 14 15 "marvell,armada-8k-gpio" should be used for the Armada 7K and 8K 16 SoCs (either from AP or CP), see 17 Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt 18 for specific details about the offset property. 19 20- reg: Address and length of the register set for the device. Only one 21 entry is expected, except for the "marvell,armadaxp-gpio" variant 22 for which two entries are expected: one for the general registers, 23 one for the per-cpu registers. Not used for marvell,armada-8k-gpio. 24 25- interrupts: The list of interrupts that are used for all the pins 26 managed by this GPIO bank. There can be more than one interrupt 27 (example: 1 interrupt per 8 pins on Armada XP, which means 4 28 interrupts per bank of 32 GPIOs). 29 30- interrupt-controller: identifies the node as an interrupt controller 31 32- #interrupt-cells: specifies the number of cells needed to encode an 33 interrupt source. Should be two. 34 The first cell is the GPIO number. 35 The second cell is used to specify flags: 36 bits[3:0] trigger type and level flags: 37 1 = low-to-high edge triggered. 38 2 = high-to-low edge triggered. 39 4 = active high level-sensitive. 40 8 = active low level-sensitive. 41 42- gpio-controller: marks the device node as a gpio controller 43 44- ngpios: number of GPIOs this controller has 45 46- #gpio-cells: Should be two. The first cell is the pin number. The 47 second cell is reserved for flags, unused at the moment. 48 49Optional properties: 50 51In order to use the GPIO lines in PWM mode, some additional optional 52properties are required. 53 54- compatible: Must contain "marvell,armada-370-gpio" 55 56- reg: an additional register set is needed, for the GPIO Blink 57 Counter on/off registers. 58 59- reg-names: Must contain an entry "pwm" corresponding to the 60 additional register range needed for PWM operation. 61 62- #pwm-cells: Should be two. The first cell is the GPIO line number. The 63 second cell is the period in nanoseconds. 64 65- clocks: Must be a phandle to the clock for the GPIO controller. 66 67Example: 68 69 gpio0: gpio@d0018100 { 70 compatible = "marvell,armadaxp-gpio"; 71 reg = <0xd0018100 0x40>, 72 <0xd0018800 0x30>; 73 ngpios = <32>; 74 gpio-controller; 75 #gpio-cells = <2>; 76 interrupt-controller; 77 #interrupt-cells = <2>; 78 interrupts = <16>, <17>, <18>, <19>; 79 }; 80 81 gpio1: gpio@18140 { 82 compatible = "marvell,armada-370-gpio"; 83 reg = <0x18140 0x40>, <0x181c8 0x08>; 84 reg-names = "gpio", "pwm"; 85 ngpios = <17>; 86 gpio-controller; 87 #gpio-cells = <2>; 88 #pwm-cells = <2>; 89 interrupt-controller; 90 #interrupt-cells = <2>; 91 interrupts = <87>, <88>, <89>; 92 clocks = <&coreclk 0>; 93 }; 94