1* General Purpose Input Output (GPIO) bus. 2 3Properties: 4- compatible: "cavium,octeon-3860-gpio" 5 6 Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs. 7 8- reg: The base address of the GPIO unit's register bank. 9 10- gpio-controller: This is a GPIO controller. 11 12- #gpio-cells: Must be <2>. The first cell is the GPIO pin. 13 14- interrupt-controller: The GPIO controller is also an interrupt 15 controller, many of its pins may be configured as an interrupt 16 source. 17 18- #interrupt-cells: Must be <2>. The first cell is the GPIO pin 19 connected to the interrupt source. The second cell is the interrupt 20 triggering protocol and may have one of four values: 21 1 - edge triggered on the rising edge. 22 2 - edge triggered on the falling edge 23 4 - level triggered active high. 24 8 - level triggered active low. 25 26- interrupts: Interrupt routing for each pin. 27 28Example: 29 30 gpio-controller@1070000000800 { 31 #gpio-cells = <2>; 32 compatible = "cavium,octeon-3860-gpio"; 33 reg = <0x10700 0x00000800 0x0 0x100>; 34 gpio-controller; 35 /* Interrupts are specified by two parts: 36 * 1) GPIO pin number (0..15) 37 * 2) Triggering (1 - edge rising 38 * 2 - edge falling 39 * 4 - level active high 40 * 8 - level active low) 41 */ 42 interrupt-controller; 43 #interrupt-cells = <2>; 44 /* The GPIO pin connect to 16 consecutive CUI bits */ 45 interrupts = <0 16>, <0 17>, <0 18>, <0 19>, 46 <0 20>, <0 21>, <0 22>, <0 23>, 47 <0 24>, <0 25>, <0 26>, <0 27>, 48 <0 28>, <0 29>, <0 30>, <0 31>; 49 }; 50