1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/gpio/aspeed,sgpio.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Aspeed SGPIO controller 8 9maintainers: 10 - Andrew Jeffery <andrew@aj.id.au> 11 12description: 13 This SGPIO controller is for ASPEED AST2400, AST2500 and AST2600 SoC, 14 AST2600 have two sgpio master one with 128 pins another one with 80 pins, 15 AST2500/AST2400 have one sgpio master with 80 pins. Each of the Serial 16 GPIO pins can be programmed to support the following options 17 - Support interrupt option for each input port and various interrupt 18 sensitivity option (level-high, level-low, edge-high, edge-low) 19 - Support reset tolerance option for each output port 20 - Directly connected to APB bus and its shift clock is from APB bus clock 21 divided by a programmable value. 22 - Co-work with external signal-chained TTL components (74LV165/74LV595) 23 24properties: 25 compatible: 26 enum: 27 - aspeed,ast2400-sgpio 28 - aspeed,ast2500-sgpio 29 - aspeed,ast2600-sgpiom 30 31 reg: 32 maxItems: 1 33 34 gpio-controller: true 35 36 '#gpio-cells': 37 const: 2 38 39 interrupts: 40 maxItems: 1 41 42 interrupt-controller: true 43 44 clocks: 45 maxItems: 1 46 47 ngpios: true 48 49 bus-frequency: true 50 51required: 52 - compatible 53 - reg 54 - gpio-controller 55 - '#gpio-cells' 56 - interrupts 57 - interrupt-controller 58 - ngpios 59 - clocks 60 - bus-frequency 61 62additionalProperties: false 63 64examples: 65 - | 66 #include <dt-bindings/clock/aspeed-clock.h> 67 sgpio: sgpio@1e780200 { 68 #gpio-cells = <2>; 69 compatible = "aspeed,ast2500-sgpio"; 70 gpio-controller; 71 interrupts = <40>; 72 reg = <0x1e780200 0x0100>; 73 clocks = <&syscon ASPEED_CLK_APB>; 74 interrupt-controller; 75 ngpios = <80>; 76 bus-frequency = <12000000>; 77 }; 78