xref: /freebsd/sys/contrib/device-tree/Bindings/firmware/nvidia,tegra186-bpmp.yaml (revision 5b56413d04e608379c9a306373554a8e4d321bc0) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/firmware/nvidia,tegra186-bpmp.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra Boot and Power Management Processor (BPMP)
8
9maintainers:
10  - Thierry Reding <thierry.reding@gmail.com>
11  - Jon Hunter <jonathanh@nvidia.com>
12
13description: |
14  The BPMP is a specific processor in Tegra chip, which is designed for
15  booting process handling and offloading the power management, clock
16  management, and reset control tasks from the CPU. The binding document
17  defines the resources that would be used by the BPMP firmware driver,
18  which can create the interprocessor communication (IPC) between the
19  CPU and BPMP.
20
21  This node is a mailbox consumer. See the following files for details
22  of the mailbox subsystem, and the specifiers implemented by the
23  relevant provider(s):
24
25    - .../mailbox/mailbox.txt
26    - .../mailbox/nvidia,tegra186-hsp.yaml
27
28  This node is a clock, power domain, and reset provider. See the
29  following files for general documentation of those features, and the
30  specifiers implemented by this node:
31
32    - .../clock/clock-bindings.txt
33    - <dt-bindings/clock/tegra186-clock.h>
34    - ../power/power-domain.yaml
35    - <dt-bindings/power/tegra186-powergate.h>
36    - .../reset/reset.txt
37    - <dt-bindings/reset/tegra186-reset.h>
38
39  The BPMP implements some services which must be represented by
40  separate nodes. For example, it can provide access to certain I2C
41  controllers, and the I2C bindings represent each I2C controller as a
42  device tree node. Such nodes should be nested directly inside the main
43  BPMP node.
44
45  Software can determine whether a child node of the BPMP node
46  represents a device by checking for a compatible property. Any node
47  with a compatible property represents a device that can be
48  instantiated. Nodes without a compatible property may be used to
49  provide configuration information regarding the BPMP itself, although
50  no such configuration nodes are currently defined by this binding.
51
52  The BPMP firmware defines no single global name-/numbering-space for
53  such services. Put another way, the numbering scheme for I2C buses is
54  distinct from the numbering scheme for any other service the BPMP may
55  provide (e.g. a future hypothetical SPI bus service). As such, child
56  device nodes will have no reg property, and the BPMP node will have no
57  "#address-cells" or "#size-cells" property.
58
59  The shared memory area for the IPC TX and RX between CPU and BPMP are
60  predefined and work on top of either sysram, which is an SRAM inside the
61  chip, or in normal SDRAM.
62  See ".../sram/sram.yaml" for the bindings for the SRAM case.
63  See "../reserved-memory/nvidia,tegra264-bpmp-shmem.yaml" for bindings for
64  the SDRAM case.
65
66properties:
67  compatible:
68    oneOf:
69      - items:
70          - enum:
71              - nvidia,tegra194-bpmp
72              - nvidia,tegra234-bpmp
73          - const: nvidia,tegra186-bpmp
74      - const: nvidia,tegra186-bpmp
75
76  mboxes:
77    description: A phandle and channel specifier for the mailbox used to
78      communicate with the BPMP.
79    maxItems: 1
80
81  shmem:
82    description: List of the phandle to the TX and RX shared memory area
83      that the IPC between CPU and BPMP is based on.
84    minItems: 2
85    maxItems: 2
86
87  memory-region:
88    description: phandle to reserved memory region used for IPC between
89      CPU-NS and BPMP.
90    maxItems: 1
91
92  "#clock-cells":
93    const: 1
94
95  "#power-domain-cells":
96    const: 1
97
98  "#reset-cells":
99    const: 1
100
101  interconnects:
102    items:
103      - description: memory read client
104      - description: memory write client
105      - description: DMA read client
106      - description: DMA write client
107
108  interconnect-names:
109    items:
110      - const: read
111      - const: write
112      - const: dma-mem # dma-read
113      - const: dma-write
114
115  iommus:
116    maxItems: 1
117
118  i2c:
119    type: object
120
121  thermal:
122    type: object
123
124additionalProperties: false
125
126oneOf:
127  - required:
128      - memory-region
129  - required:
130      - shmem
131
132required:
133  - compatible
134  - mboxes
135  - "#clock-cells"
136  - "#power-domain-cells"
137  - "#reset-cells"
138
139examples:
140  - |
141    #include <dt-bindings/interrupt-controller/arm-gic.h>
142    #include <dt-bindings/mailbox/tegra186-hsp.h>
143    #include <dt-bindings/memory/tegra186-mc.h>
144
145    hsp_top0: hsp@3c00000 {
146        compatible = "nvidia,tegra186-hsp";
147        reg = <0x03c00000 0xa0000>;
148        interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
149        interrupt-names = "doorbell";
150        #mbox-cells = <2>;
151    };
152
153    sram@30000000 {
154        compatible = "nvidia,tegra186-sysram", "mmio-sram";
155        reg = <0x30000000 0x50000>;
156        #address-cells = <1>;
157        #size-cells = <1>;
158        ranges = <0x0 0x30000000 0x50000>;
159
160        cpu_bpmp_tx: sram@4e000 {
161            reg = <0x4e000 0x1000>;
162            label = "cpu-bpmp-tx";
163            pool;
164        };
165
166        cpu_bpmp_rx: sram@4f000 {
167            reg = <0x4f000 0x1000>;
168            label = "cpu-bpmp-rx";
169            pool;
170        };
171    };
172
173    bpmp {
174        compatible = "nvidia,tegra186-bpmp";
175        interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
176                        <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
177                        <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
178                        <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
179        interconnect-names = "read", "write", "dma-mem", "dma-write";
180        iommus = <&smmu TEGRA186_SID_BPMP>;
181        mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>;
182        shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
183        #clock-cells = <1>;
184        #power-domain-cells = <1>;
185        #reset-cells = <1>;
186
187        i2c {
188            compatible = "nvidia,tegra186-bpmp-i2c";
189            nvidia,bpmp-bus-id = <5>;
190            #address-cells = <1>;
191            #size-cells = <0>;
192        };
193
194        thermal {
195            compatible = "nvidia,tegra186-bpmp-thermal";
196            #thermal-sensor-cells = <1>;
197        };
198    };
199
200  - |
201    #include <dt-bindings/mailbox/tegra186-hsp.h>
202
203    bpmp {
204        compatible = "nvidia,tegra186-bpmp";
205        interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
206                        <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
207                        <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
208                        <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
209        interconnect-names = "read", "write", "dma-mem", "dma-write";
210        mboxes = <&hsp_top1 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>;
211        memory-region = <&dram_cpu_bpmp_mail>;
212        #clock-cells = <1>;
213        #power-domain-cells = <1>;
214        #reset-cells = <1>;
215    };
216