1NVIDIA Tegra Boot and Power Management Processor (BPMP) 2 3The BPMP is a specific processor in Tegra chip, which is designed for 4booting process handling and offloading the power management, clock 5management, and reset control tasks from the CPU. The binding document 6defines the resources that would be used by the BPMP firmware driver, 7which can create the interprocessor communication (IPC) between the CPU 8and BPMP. 9 10Required properties: 11- compatible 12 Array of strings 13 One of: 14 - "nvidia,tegra186-bpmp" 15- mboxes : The phandle of mailbox controller and the mailbox specifier. 16- shmem : List of the phandle of the TX and RX shared memory area that 17 the IPC between CPU and BPMP is based on. 18- #clock-cells : Should be 1. 19- #power-domain-cells : Should be 1. 20- #reset-cells : Should be 1. 21 22This node is a mailbox consumer. See the following files for details of 23the mailbox subsystem, and the specifiers implemented by the relevant 24provider(s): 25 26- .../mailbox/mailbox.txt 27- .../mailbox/nvidia,tegra186-hsp.txt 28 29This node is a clock, power domain, and reset provider. See the following 30files for general documentation of those features, and the specifiers 31implemented by this node: 32 33- .../clock/clock-bindings.txt 34- <dt-bindings/clock/tegra186-clock.h> 35- ../power/power-domain.yaml 36- <dt-bindings/power/tegra186-powergate.h> 37- .../reset/reset.txt 38- <dt-bindings/reset/tegra186-reset.h> 39 40The BPMP implements some services which must be represented by separate nodes. 41For example, it can provide access to certain I2C controllers, and the I2C 42bindings represent each I2C controller as a device tree node. Such nodes should 43be nested directly inside the main BPMP node. 44 45Software can determine whether a child node of the BPMP node represents a device 46by checking for a compatible property. Any node with a compatible property 47represents a device that can be instantiated. Nodes without a compatible 48property may be used to provide configuration information regarding the BPMP 49itself, although no such configuration nodes are currently defined by this 50binding. 51 52The BPMP firmware defines no single global name-/numbering-space for such 53services. Put another way, the numbering scheme for I2C buses is distinct from 54the numbering scheme for any other service the BPMP may provide (e.g. a future 55hypothetical SPI bus service). As such, child device nodes will have no reg 56property, and the BPMP node will have no #address-cells or #size-cells property. 57 58The shared memory bindings for BPMP 59----------------------------------- 60 61The shared memory area for the IPC TX and RX between CPU and BPMP are 62predefined and work on top of sysram, which is an SRAM inside the chip. 63 64See ".../sram/sram.txt" for the bindings. 65 66Example: 67 68hsp_top0: hsp@3c00000 { 69 ... 70 #mbox-cells = <2>; 71}; 72 73sysram@30000000 { 74 compatible = "nvidia,tegra186-sysram", "mmio-sram"; 75 reg = <0x0 0x30000000 0x0 0x50000>; 76 #address-cells = <2>; 77 #size-cells = <2>; 78 ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 79 80 cpu_bpmp_tx: shmem@4e000 { 81 compatible = "nvidia,tegra186-bpmp-shmem"; 82 reg = <0x0 0x4e000 0x0 0x1000>; 83 label = "cpu-bpmp-tx"; 84 pool; 85 }; 86 87 cpu_bpmp_rx: shmem@4f000 { 88 compatible = "nvidia,tegra186-bpmp-shmem"; 89 reg = <0x0 0x4f000 0x0 0x1000>; 90 label = "cpu-bpmp-rx"; 91 pool; 92 }; 93}; 94 95bpmp { 96 compatible = "nvidia,tegra186-bpmp"; 97 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>; 98 shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; 99 #clock-cells = <1>; 100 #power-domain-cells = <1>; 101 #reset-cells = <1>; 102 103 i2c { 104 compatible = "..."; 105 ... 106 }; 107}; 108