1Intel Service Layer Driver for Stratix10 SoC 2============================================ 3Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard 4processor system (HPS) and Secure Device Manager (SDM). When the FPGA is 5configured from HPS, there needs to be a way for HPS to notify SDM the 6location and size of the configuration data. Then SDM will get the 7configuration data from that location and perform the FPGA configuration. 8 9To meet the whole system security needs and support virtual machine requesting 10communication with SDM, only the secure world of software (EL3, Exception 11Layer 3) can interface with SDM. All software entities running on other 12exception layers must channel through the EL3 software whenever it needs 13service from SDM. 14 15Intel Stratix10 service layer driver, running at privileged exception level 16(EL1, Exception Layer 1), interfaces with the service providers and provides 17the services for FPGA configuration, QSPI, Crypto and warm reset. Service layer 18driver also manages secure monitor call (SMC) to communicate with secure monitor 19code running in EL3. 20 21Required properties: 22------------------- 23The svc node has the following mandatory properties, must be located under 24the firmware node. 25 26- compatible: "intel,stratix10-svc" or "intel,agilex-svc" 27- method: smc or hvc 28 smc - Secure Monitor Call 29 hvc - Hypervisor Call 30- memory-region: 31 phandle to the reserved memory node. See 32 Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt 33 for details 34 35Example: 36------- 37 38 reserved-memory { 39 #address-cells = <2>; 40 #size-cells = <2>; 41 ranges; 42 43 service_reserved: svcbuffer@0 { 44 compatible = "shared-dma-pool"; 45 reg = <0x0 0x0 0x0 0x1000000>; 46 alignment = <0x1000>; 47 no-map; 48 }; 49 }; 50 51 firmware { 52 svc { 53 compatible = "intel,stratix10-svc"; 54 method = "smc"; 55 memory-region = <&service_reserved>; 56 }; 57 }; 58