1Altera SoCFPGA ECC Manager 2This driver uses the EDAC framework to implement the SOCFPGA ECC Manager. 3The ECC Manager counts and corrects single bit errors and counts/handles 4double bit errors which are uncorrectable. 5 6Cyclone5 and Arria5 ECC Manager 7Required Properties: 8- compatible : Should be "altr,socfpga-ecc-manager" 9- #address-cells: must be 1 10- #size-cells: must be 1 11- ranges : standard definition, should translate from local addresses 12 13Subcomponents: 14 15L2 Cache ECC 16Required Properties: 17- compatible : Should be "altr,socfpga-l2-ecc" 18- reg : Address and size for ECC error interrupt clear registers. 19- interrupts : Should be single bit error interrupt, then double bit error 20 interrupt. Note the rising edge type. 21 22On Chip RAM ECC 23Required Properties: 24- compatible : Should be "altr,socfpga-ocram-ecc" 25- reg : Address and size for ECC error interrupt clear registers. 26- iram : phandle to On-Chip RAM definition. 27- interrupts : Should be single bit error interrupt, then double bit error 28 interrupt. Note the rising edge type. 29 30Example: 31 32 eccmgr: eccmgr@ffd08140 { 33 compatible = "altr,socfpga-ecc-manager"; 34 #address-cells = <1>; 35 #size-cells = <1>; 36 ranges; 37 38 l2-ecc@ffd08140 { 39 compatible = "altr,socfpga-l2-ecc"; 40 reg = <0xffd08140 0x4>; 41 interrupts = <0 36 1>, <0 37 1>; 42 }; 43 44 ocram-ecc@ffd08144 { 45 compatible = "altr,socfpga-ocram-ecc"; 46 reg = <0xffd08144 0x4>; 47 iram = <&ocram>; 48 interrupts = <0 178 1>, <0 179 1>; 49 }; 50 }; 51 52Arria10 SoCFPGA ECC Manager 53The Arria10 SoC ECC Manager handles the IRQs for each peripheral 54in a shared register instead of individual IRQs like the Cyclone5 55and Arria5. Therefore the device tree is different as well. 56 57Required Properties: 58- compatible : Should be "altr,socfpga-a10-ecc-manager" 59- altr,sysgr-syscon : phandle to Arria10 System Manager Block 60 containing the ECC manager registers. 61- #address-cells: must be 1 62- #size-cells: must be 1 63- interrupts : Should be single bit error interrupt, then double bit error 64 interrupt. 65- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller 66- #interrupt-cells : must be set to 2. 67- ranges : standard definition, should translate from local addresses 68 69Subcomponents: 70 71L2 Cache ECC 72Required Properties: 73- compatible : Should be "altr,socfpga-a10-l2-ecc" 74- reg : Address and size for ECC error interrupt clear registers. 75- interrupts : Should be single bit error interrupt, then double bit error 76 interrupt, in this order. 77 78On-Chip RAM ECC 79Required Properties: 80- compatible : Should be "altr,socfpga-a10-ocram-ecc" 81- reg : Address and size for ECC block registers. 82- interrupts : Should be single bit error interrupt, then double bit error 83 interrupt, in this order. 84 85Ethernet FIFO ECC 86Required Properties: 87- compatible : Should be "altr,socfpga-eth-mac-ecc" 88- reg : Address and size for ECC block registers. 89- altr,ecc-parent : phandle to parent Ethernet node. 90- interrupts : Should be single bit error interrupt, then double bit error 91 interrupt, in this order. 92 93NAND FIFO ECC 94Required Properties: 95- compatible : Should be "altr,socfpga-nand-ecc" 96- reg : Address and size for ECC block registers. 97- altr,ecc-parent : phandle to parent NAND node. 98- interrupts : Should be single bit error interrupt, then double bit error 99 interrupt, in this order. 100 101DMA FIFO ECC 102Required Properties: 103- compatible : Should be "altr,socfpga-dma-ecc" 104- reg : Address and size for ECC block registers. 105- altr,ecc-parent : phandle to parent DMA node. 106- interrupts : Should be single bit error interrupt, then double bit error 107 interrupt, in this order. 108 109USB FIFO ECC 110Required Properties: 111- compatible : Should be "altr,socfpga-usb-ecc" 112- reg : Address and size for ECC block registers. 113- altr,ecc-parent : phandle to parent USB node. 114- interrupts : Should be single bit error interrupt, then double bit error 115 interrupt, in this order. 116 117QSPI FIFO ECC 118Required Properties: 119- compatible : Should be "altr,socfpga-qspi-ecc" 120- reg : Address and size for ECC block registers. 121- altr,ecc-parent : phandle to parent QSPI node. 122- interrupts : Should be single bit error interrupt, then double bit error 123 interrupt, in this order. 124 125SDMMC FIFO ECC 126Required Properties: 127- compatible : Should be "altr,socfpga-sdmmc-ecc" 128- reg : Address and size for ECC block registers. 129- altr,ecc-parent : phandle to parent SD/MMC node. 130- interrupts : Should be single bit error interrupt, then double bit error 131 interrupt, in this order for port A, and then single bit error interrupt, 132 then double bit error interrupt in this order for port B. 133 134Example: 135 136 eccmgr: eccmgr@ffd06000 { 137 compatible = "altr,socfpga-a10-ecc-manager"; 138 altr,sysmgr-syscon = <&sysmgr>; 139 #address-cells = <1>; 140 #size-cells = <1>; 141 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>, 142 <0 0 IRQ_TYPE_LEVEL_HIGH>; 143 interrupt-controller; 144 #interrupt-cells = <2>; 145 ranges; 146 147 l2-ecc@ffd06010 { 148 compatible = "altr,socfpga-a10-l2-ecc"; 149 reg = <0xffd06010 0x4>; 150 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>, 151 <32 IRQ_TYPE_LEVEL_HIGH>; 152 }; 153 154 ocram-ecc@ff8c3000 { 155 compatible = "altr,socfpga-a10-ocram-ecc"; 156 reg = <0xff8c3000 0x90>; 157 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>, 158 <33 IRQ_TYPE_LEVEL_HIGH> ; 159 }; 160 161 emac0-rx-ecc@ff8c0800 { 162 compatible = "altr,socfpga-eth-mac-ecc"; 163 reg = <0xff8c0800 0x400>; 164 altr,ecc-parent = <&gmac0>; 165 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>, 166 <36 IRQ_TYPE_LEVEL_HIGH>; 167 }; 168 169 emac0-tx-ecc@ff8c0c00 { 170 compatible = "altr,socfpga-eth-mac-ecc"; 171 reg = <0xff8c0c00 0x400>; 172 altr,ecc-parent = <&gmac0>; 173 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>, 174 <37 IRQ_TYPE_LEVEL_HIGH>; 175 }; 176 177 nand-buf-ecc@ff8c2000 { 178 compatible = "altr,socfpga-nand-ecc"; 179 reg = <0xff8c2000 0x400>; 180 altr,ecc-parent = <&nand>; 181 interrupts = <11 IRQ_TYPE_LEVEL_HIGH>, 182 <43 IRQ_TYPE_LEVEL_HIGH>; 183 }; 184 185 nand-rd-ecc@ff8c2400 { 186 compatible = "altr,socfpga-nand-ecc"; 187 reg = <0xff8c2400 0x400>; 188 altr,ecc-parent = <&nand>; 189 interrupts = <13 IRQ_TYPE_LEVEL_HIGH>, 190 <45 IRQ_TYPE_LEVEL_HIGH>; 191 }; 192 193 nand-wr-ecc@ff8c2800 { 194 compatible = "altr,socfpga-nand-ecc"; 195 reg = <0xff8c2800 0x400>; 196 altr,ecc-parent = <&nand>; 197 interrupts = <12 IRQ_TYPE_LEVEL_HIGH>, 198 <44 IRQ_TYPE_LEVEL_HIGH>; 199 }; 200 201 dma-ecc@ff8c8000 { 202 compatible = "altr,socfpga-dma-ecc"; 203 reg = <0xff8c8000 0x400>; 204 altr,ecc-parent = <&pdma>; 205 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>, 206 <42 IRQ_TYPE_LEVEL_HIGH>; 207 208 usb0-ecc@ff8c8800 { 209 compatible = "altr,socfpga-usb-ecc"; 210 reg = <0xff8c8800 0x400>; 211 altr,ecc-parent = <&usb0>; 212 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>, 213 <34 IRQ_TYPE_LEVEL_HIGH>; 214 }; 215 216 qspi-ecc@ff8c8400 { 217 compatible = "altr,socfpga-qspi-ecc"; 218 reg = <0xff8c8400 0x400>; 219 altr,ecc-parent = <&qspi>; 220 interrupts = <14 IRQ_TYPE_LEVEL_HIGH>, 221 <46 IRQ_TYPE_LEVEL_HIGH>; 222 }; 223 224 sdmmc-ecc@ff8c2c00 { 225 compatible = "altr,socfpga-sdmmc-ecc"; 226 reg = <0xff8c2c00 0x400>; 227 altr,ecc-parent = <&mmc>; 228 interrupts = <15 IRQ_TYPE_LEVEL_HIGH>, 229 <47 IRQ_TYPE_LEVEL_HIGH>, 230 <16 IRQ_TYPE_LEVEL_HIGH>, 231 <48 IRQ_TYPE_LEVEL_HIGH>; 232 }; 233 }; 234 235Stratix10 SoCFPGA ECC Manager (ARM64) 236The Stratix10 SoC ECC Manager handles the IRQs for each peripheral 237in a shared register similar to the Arria10. However, Stratix10 ECC 238requires access to registers that can only be read from Secure Monitor 239with SMC calls. Therefore the device tree is slightly different. Note 240that only 1 interrupt is sent in Stratix10 because the double bit errors 241are treated as SErrors in ARM64 instead of IRQs in ARM32. 242 243Required Properties: 244- compatible : Should be "altr,socfpga-s10-ecc-manager" 245- altr,sysgr-syscon : phandle to Stratix10 System Manager Block 246 containing the ECC manager registers. 247- interrupts : Should be single bit error interrupt. 248- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller 249- #interrupt-cells : must be set to 2. 250- #address-cells: must be 1 251- #size-cells: must be 1 252- ranges : standard definition, should translate from local addresses 253 254Subcomponents: 255 256SDRAM ECC 257Required Properties: 258- compatible : Should be "altr,sdram-edac-s10" 259- interrupts : Should be single bit error interrupt. 260 261On-Chip RAM ECC 262Required Properties: 263- compatible : Should be "altr,socfpga-s10-ocram-ecc" 264- reg : Address and size for ECC block registers. 265- altr,ecc-parent : phandle to parent OCRAM node. 266- interrupts : Should be single bit error interrupt. 267 268Ethernet FIFO ECC 269Required Properties: 270- compatible : Should be "altr,socfpga-s10-eth-mac-ecc" 271- reg : Address and size for ECC block registers. 272- altr,ecc-parent : phandle to parent Ethernet node. 273- interrupts : Should be single bit error interrupt. 274 275NAND FIFO ECC 276Required Properties: 277- compatible : Should be "altr,socfpga-s10-nand-ecc" 278- reg : Address and size for ECC block registers. 279- altr,ecc-parent : phandle to parent NAND node. 280- interrupts : Should be single bit error interrupt. 281 282DMA FIFO ECC 283Required Properties: 284- compatible : Should be "altr,socfpga-s10-dma-ecc" 285- reg : Address and size for ECC block registers. 286- altr,ecc-parent : phandle to parent DMA node. 287- interrupts : Should be single bit error interrupt. 288 289USB FIFO ECC 290Required Properties: 291- compatible : Should be "altr,socfpga-s10-usb-ecc" 292- reg : Address and size for ECC block registers. 293- altr,ecc-parent : phandle to parent USB node. 294- interrupts : Should be single bit error interrupt. 295 296SDMMC FIFO ECC 297Required Properties: 298- compatible : Should be "altr,socfpga-s10-sdmmc-ecc" 299- reg : Address and size for ECC block registers. 300- altr,ecc-parent : phandle to parent SD/MMC node. 301- interrupts : Should be single bit error interrupt for port A 302 and then single bit error interrupt for port B. 303 304Example: 305 306 eccmgr { 307 compatible = "altr,socfpga-s10-ecc-manager"; 308 altr,sysmgr-syscon = <&sysmgr>; 309 #address-cells = <1>; 310 #size-cells = <1>; 311 interrupts = <0 15 4>; 312 interrupt-controller; 313 #interrupt-cells = <2>; 314 ranges; 315 316 sdramedac { 317 compatible = "altr,sdram-edac-s10"; 318 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 319 }; 320 321 ocram-ecc@ff8cc000 { 322 compatible = "altr,socfpga-s10-ocram-ecc"; 323 reg = <ff8cc000 0x100>; 324 altr,ecc-parent = <&ocram>; 325 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; 326 }; 327 328 emac0-rx-ecc@ff8c0000 { 329 compatible = "altr,socfpga-s10-eth-mac-ecc"; 330 reg = <0xff8c0000 0x100>; 331 altr,ecc-parent = <&gmac0>; 332 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 333 }; 334 335 emac0-tx-ecc@ff8c0400 { 336 compatible = "altr,socfpga-s10-eth-mac-ecc"; 337 reg = <0xff8c0400 0x100>; 338 altr,ecc-parent = <&gmac0>; 339 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>' 340 }; 341 342 nand-buf-ecc@ff8c8000 { 343 compatible = "altr,socfpga-s10-nand-ecc"; 344 reg = <0xff8c8000 0x100>; 345 altr,ecc-parent = <&nand>; 346 interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; 347 }; 348 349 nand-rd-ecc@ff8c8400 { 350 compatible = "altr,socfpga-s10-nand-ecc"; 351 reg = <0xff8c8400 0x100>; 352 altr,ecc-parent = <&nand>; 353 interrupts = <13 IRQ_TYPE_LEVEL_HIGH>; 354 }; 355 356 nand-wr-ecc@ff8c8800 { 357 compatible = "altr,socfpga-s10-nand-ecc"; 358 reg = <0xff8c8800 0x100>; 359 altr,ecc-parent = <&nand>; 360 interrupts = <12 IRQ_TYPE_LEVEL_HIGH>; 361 }; 362 363 dma-ecc@ff8c9000 { 364 compatible = "altr,socfpga-s10-dma-ecc"; 365 reg = <0xff8c9000 0x100>; 366 altr,ecc-parent = <&pdma>; 367 interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; 368 369 usb0-ecc@ff8c4000 { 370 compatible = "altr,socfpga-s10-usb-ecc"; 371 reg = <0xff8c4000 0x100>; 372 altr,ecc-parent = <&usb0>; 373 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; 374 }; 375 376 sdmmc-ecc@ff8c8c00 { 377 compatible = "altr,socfpga-s10-sdmmc-ecc"; 378 reg = <0xff8c8c00 0x100>; 379 altr,ecc-parent = <&mmc>; 380 interrupts = <14 IRQ_TYPE_LEVEL_HIGH>, 381 <15 IRQ_TYPE_LEVEL_HIGH>; 382 }; 383 }; 384