xref: /freebsd/sys/contrib/device-tree/Bindings/dpll/microchip,zl30731.yaml (revision 833e5d42ab135b0238e61c5b3c19b8619677cbfa)

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dpll/microchip,zl30731.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Microchip Azurite DPLL device

maintainers:
  - Ivan Vecera <ivecera@redhat.com>

description:
  Microchip Azurite DPLL (ZL3073x) is a family of DPLL devices that
  provides up to 5 independent DPLL channels, up to 10 differential or
  single-ended inputs and 10 differential or 20 single-ended outputs.
  These devices support both I2C and SPI interfaces.

properties:
  compatible:
    enum:
      - microchip,zl30731
      - microchip,zl30732
      - microchip,zl30733
      - microchip,zl30734
      - microchip,zl30735

  reg:
    maxItems: 1

required:
  - compatible
  - reg

allOf:
  - $ref: /schemas/dpll/dpll-device.yaml#
  - $ref: /schemas/spi/spi-peripheral-props.yaml#

unevaluatedProperties: false

examples:
  - |
    i2c {
      #address-cells = <1>;
      #size-cells = <0>;

      dpll@70 {
        compatible = "microchip,zl30732";
        reg = <0x70>;
        dpll-types = "pps", "eec";

        input-pins {
          #address-cells = <1>;
          #size-cells = <0>;

          pin@0 { /* REF0P */
            reg = <0>;
            connection-type = "ext";
            label = "Input 0";
            supported-frequencies-hz = /bits/ 64 <1 1000>;
          };
        };

        output-pins {
          #address-cells = <1>;
          #size-cells = <0>;

          pin@3 { /* OUT1N */
            reg = <3>;
            connection-type = "gnss";
            esync-control;
            label = "Output 1";
            supported-frequencies-hz = /bits/ 64 <1 10000>;
          };
        };
      };
    };
  - |
    spi {
      #address-cells = <1>;
      #size-cells = <0>;

      dpll@70 {
        compatible = "microchip,zl30731";
        reg = <0x70>;
        spi-max-frequency = <12500000>;

        dpll-types = "pps";

        input-pins {
          #address-cells = <1>;
          #size-cells = <0>;

          pin@0 { /* REF0P */
            reg = <0>;
            connection-type = "ext";
            label = "Input 0";
            supported-frequencies-hz = /bits/ 64 <1 1000>;
          };
        };

        output-pins {
          #address-cells = <1>;
          #size-cells = <0>;

          pin@3 { /* OUT1N */
            reg = <3>;
            connection-type = "gnss";
            esync-control;
            label = "Output 1";
            supported-frequencies-hz = /bits/ 64 <1 10000>;
          };
        };
      };
    };
...