1*c66ec88fSEmmanuel VadotXilinx ZynqMP DMA engine, it does support memory to memory transfers, 2*c66ec88fSEmmanuel Vadotmemory to device and device to memory transfers. It also has flow 3*c66ec88fSEmmanuel Vadotcontrol and rate control support for slave/peripheral dma access. 4*c66ec88fSEmmanuel Vadot 5*c66ec88fSEmmanuel VadotRequired properties: 6*c66ec88fSEmmanuel Vadot- compatible : Should be "xlnx,zynqmp-dma-1.0" 7*c66ec88fSEmmanuel Vadot- reg : Memory map for gdma/adma module access. 8*c66ec88fSEmmanuel Vadot- interrupts : Should contain DMA channel interrupt. 9*c66ec88fSEmmanuel Vadot- xlnx,bus-width : Axi buswidth in bits. Should contain 128 or 64 10*c66ec88fSEmmanuel Vadot- clock-names : List of input clocks "clk_main", "clk_apb" 11*c66ec88fSEmmanuel Vadot (see clock bindings for details) 12*c66ec88fSEmmanuel Vadot 13*c66ec88fSEmmanuel VadotOptional properties: 14*c66ec88fSEmmanuel Vadot- dma-coherent : Present if dma operations are coherent. 15*c66ec88fSEmmanuel Vadot 16*c66ec88fSEmmanuel VadotExample: 17*c66ec88fSEmmanuel Vadot++++++++ 18*c66ec88fSEmmanuel Vadotfpd_dma_chan1: dma@fd500000 { 19*c66ec88fSEmmanuel Vadot compatible = "xlnx,zynqmp-dma-1.0"; 20*c66ec88fSEmmanuel Vadot reg = <0x0 0xFD500000 0x1000>; 21*c66ec88fSEmmanuel Vadot interrupt-parent = <&gic>; 22*c66ec88fSEmmanuel Vadot interrupts = <0 117 4>; 23*c66ec88fSEmmanuel Vadot clock-names = "clk_main", "clk_apb"; 24*c66ec88fSEmmanuel Vadot xlnx,bus-width = <128>; 25*c66ec88fSEmmanuel Vadot dma-coherent; 26*c66ec88fSEmmanuel Vadot}; 27