xref: /freebsd/sys/contrib/device-tree/Bindings/dma/ti/k3-udma.yaml (revision 8bab661a3316d8bd9b9fbd11a3b4371b91507bd2)
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (C) 2019 Texas Instruments Incorporated
3# Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
4%YAML 1.2
5---
6$id: http://devicetree.org/schemas/dma/ti/k3-udma.yaml#
7$schema: http://devicetree.org/meta-schemas/core.yaml#
8
9title: Texas Instruments K3 NAVSS Unified DMA
10
11maintainers:
12  - Peter Ujfalusi <peter.ujfalusi@gmail.com>
13
14description: |
15  The UDMA-P is intended to perform similar (but significantly upgraded)
16  functions as the packet-oriented DMA used on previous SoC devices. The UDMA-P
17  module supports the transmission and reception of various packet types.
18  The UDMA-P architecture facilitates the segmentation and reassembly of SoC DMA
19  data structure compliant packets to/from smaller data blocks that are natively
20  compatible with the specific requirements of each connected peripheral.
21  Multiple Tx and Rx channels are provided within the DMA which allow multiple
22  segmentation or reassembly operations to be ongoing. The DMA controller
23  maintains state information for each of the channels which allows packet
24  segmentation and reassembly operations to be time division multiplexed between
25  channels in order to share the underlying DMA hardware. An external DMA
26  scheduler is used to control the ordering and rate at which this multiplexing
27  occurs for Transmit operations. The ordering and rate of Receive operations
28  is indirectly controlled by the order in which blocks are pushed into the DMA
29  on the Rx PSI-L interface.
30
31  The UDMA-P also supports acting as both a UTC and UDMA-C for its internal
32  channels. Channels in the UDMA-P can be configured to be either Packet-Based
33  or Third-Party channels on a channel by channel basis.
34
35  All transfers within NAVSS is done between PSI-L source and destination
36  threads.
37  The peripherals serviced by UDMA can be PSI-L native (sa2ul, cpsw, etc) or
38  legacy, non PSI-L native peripherals. In the later case a special, small PDMA
39  is tasked to act as a bridge between the PSI-L fabric and the legacy
40  peripheral.
41
42  PDMAs can be configured via UDMAP peer registers to match with the
43  configuration of the legacy peripheral.
44
45allOf:
46  - $ref: "../dma-controller.yaml#"
47
48properties:
49  "#dma-cells":
50    minimum: 1
51    maximum: 2
52    description: |
53      The cell is the PSI-L  thread ID of the remote (to UDMAP) end.
54      Valid ranges for thread ID depends on the data movement direction:
55      for source thread IDs (rx): 0 - 0x7fff
56      for destination thread IDs (tx): 0x8000 - 0xffff
57
58      Please refer to the device documentation for the PSI-L thread map and also
59      the PSI-L peripheral chapter for the correct thread ID.
60
61      When #dma-cells is 2, the second parameter is the channel ATYPE.
62
63  compatible:
64    enum:
65      - ti,am654-navss-main-udmap
66      - ti,am654-navss-mcu-udmap
67      - ti,j721e-navss-main-udmap
68      - ti,j721e-navss-mcu-udmap
69
70  reg:
71    maxItems: 3
72
73  reg-names:
74    items:
75      - const: gcfg
76      - const: rchanrt
77      - const: tchanrt
78
79  msi-parent: true
80
81  ti,sci:
82    description: phandle to TI-SCI compatible System controller node
83    $ref: /schemas/types.yaml#/definitions/phandle
84
85  ti,sci-dev-id:
86    description: TI-SCI device id of UDMAP
87    $ref: /schemas/types.yaml#/definitions/uint32
88
89  ti,ringacc:
90    description: phandle to the ring accelerator node
91    $ref: /schemas/types.yaml#/definitions/phandle
92
93  ti,sci-rm-range-tchan:
94    description: |
95      Array of UDMA tchan resource subtypes for resource allocation for this
96      host
97    $ref: /schemas/types.yaml#/definitions/uint32-array
98    minItems: 1
99    # Should be enough
100    maxItems: 255
101
102  ti,sci-rm-range-rchan:
103    description: |
104      Array of UDMA rchan resource subtypes for resource allocation for this
105      host
106    $ref: /schemas/types.yaml#/definitions/uint32-array
107    minItems: 1
108    # Should be enough
109    maxItems: 255
110
111  ti,sci-rm-range-rflow:
112    description: |
113      Array of UDMA rflow resource subtypes for resource allocation for this
114      host
115    $ref: /schemas/types.yaml#/definitions/uint32-array
116    minItems: 1
117    # Should be enough
118    maxItems: 255
119
120required:
121  - compatible
122  - "#dma-cells"
123  - reg
124  - reg-names
125  - msi-parent
126  - ti,sci
127  - ti,sci-dev-id
128  - ti,ringacc
129  - ti,sci-rm-range-tchan
130  - ti,sci-rm-range-rchan
131  - ti,sci-rm-range-rflow
132
133if:
134  properties:
135    "#dma-cells":
136      const: 2
137then:
138  properties:
139    ti,udma-atype:
140      description: ATYPE value which should be used by non slave channels
141      $ref: /schemas/types.yaml#/definitions/uint32
142
143  required:
144    - ti,udma-atype
145
146unevaluatedProperties: false
147
148examples:
149  - |+
150    cbass_main {
151        #address-cells = <2>;
152        #size-cells = <2>;
153
154        cbass_main_navss: navss@30800000 {
155            compatible = "simple-mfd";
156            #address-cells = <2>;
157            #size-cells = <2>;
158            dma-coherent;
159            dma-ranges;
160            ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0x05000000>;
161
162            ti,sci-dev-id = <118>;
163
164            main_udmap: dma-controller@31150000 {
165                compatible = "ti,am654-navss-main-udmap";
166                reg = <0x0 0x31150000 0x0 0x100>,
167                      <0x0 0x34000000 0x0 0x100000>,
168                      <0x0 0x35000000 0x0 0x100000>;
169                reg-names = "gcfg", "rchanrt", "tchanrt";
170                #dma-cells = <1>;
171
172                ti,ringacc = <&ringacc>;
173
174                msi-parent = <&inta_main_udmass>;
175
176                ti,sci = <&dmsc>;
177                ti,sci-dev-id = <188>;
178
179                ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
180                                        <0x2>; /* TX_CHAN */
181                ti,sci-rm-range-rchan = <0x4>, /* RX_HCHAN */
182                                        <0x5>; /* RX_CHAN */
183                ti,sci-rm-range-rflow = <0x6>; /* GP RFLOW */
184            };
185        };
186    };
187