1* DMA40 DMA Controller 2 3Required properties: 4- compatible: "stericsson,dma40" 5- reg: Address range of the DMAC registers 6- reg-names: Names of the above areas to use during resource look-up 7- interrupt: Should contain the DMAC interrupt number 8- #dma-cells: must be <3> 9- memcpy-channels: Channels to be used for memcpy 10 11Optional properties: 12- dma-channels: Number of channels supported by hardware - if not present 13 the driver will attempt to obtain the information from H/W 14- disabled-channels: Channels which can not be used 15 16Example: 17 18 dma: dma-controller@801c0000 { 19 compatible = "stericsson,db8500-dma40", "stericsson,dma40"; 20 reg = <0x801C0000 0x1000 0x40010000 0x800>; 21 reg-names = "base", "lcpa"; 22 interrupt-parent = <&intc>; 23 interrupts = <0 25 0x4>; 24 25 #dma-cells = <2>; 26 memcpy-channels = <56 57 58 59 60>; 27 disabled-channels = <12>; 28 dma-channels = <8>; 29 }; 30 31Clients 32Required properties: 33- dmas: Comma separated list of dma channel requests 34- dma-names: Names of the aforementioned requested channels 35 36Each dmas request consists of 4 cells: 37 1. A phandle pointing to the DMA controller 38 2. Device signal number, the signal line for single and burst requests 39 connected from the device to the DMA40 engine 40 3. The DMA request line number (only when 'use fixed channel' is set) 41 4. A 32bit mask specifying; mode, direction and endianness 42 [NB: This list will grow] 43 0x00000001: Mode: 44 Logical channel when unset 45 Physical channel when set 46 0x00000002: Direction: 47 Memory to Device when unset 48 Device to Memory when set 49 0x00000004: Endianness: 50 Little endian when unset 51 Big endian when set 52 0x00000008: Use fixed channel: 53 Use automatic channel selection when unset 54 Use DMA request line number when set 55 0x00000010: Set channel as high priority: 56 Normal priority when unset 57 High priority when set 58 59Existing signal numbers for the DB8500 ASIC. Unless specified, the signals are 60bidirectional, i.e. the same for RX and TX operations: 61 620: SPI controller 0 631: SD/MMC controller 0 (unused) 642: SD/MMC controller 1 (unused) 653: SD/MMC controller 2 (unused) 664: I2C port 1 675: I2C port 3 686: I2C port 2 697: I2C port 4 708: Synchronous Serial Port SSP0 719: Synchronous Serial Port SSP1 7210: Multi-Channel Display Engine MCDE RX 7311: UART port 2 7412: UART port 1 7513: UART port 0 7614: Multirate Serial Port MSP2 7715: I2C port 0 7816: USB OTG in/out endpoints 7 & 15 7917: USB OTG in/out endpoints 6 & 14 8018: USB OTG in/out endpoints 5 & 13 8119: USB OTG in/out endpoints 4 & 12 8220: SLIMbus or HSI channel 0 8321: SLIMbus or HSI channel 1 8422: SLIMbus or HSI channel 2 8523: SLIMbus or HSI channel 3 8624: Multimedia DSP SXA0 8725: Multimedia DSP SXA1 8826: Multimedia DSP SXA2 8927: Multimedia DSP SXA3 9028: SD/MM controller 2 9129: SD/MM controller 0 9230: MSP port 1 on DB8500 v1, MSP port 3 on DB8500 v2 9331: MSP port 0 or SLIMbus channel 0 9432: SD/MM controller 1 9533: SPI controller 2 9634: i2c3 RX2 TX2 9735: SPI controller 1 9836: USB OTG in/out endpoints 3 & 11 9937: USB OTG in/out endpoints 2 & 10 10038: USB OTG in/out endpoints 1 & 9 10139: USB OTG in/out endpoints 8 10240: SPI controller 3 10341: SD/MM controller 3 10442: SD/MM controller 4 10543: SD/MM controller 5 10644: Multimedia DSP SXA4 10745: Multimedia DSP SXA5 10846: SLIMbus channel 8 or Multimedia DSP SXA6 10947: SLIMbus channel 9 or Multimedia DSP SXA7 11048: Crypto Accelerator 1 11149: Crypto Accelerator 1 TX or Hash Accelerator 1 TX 11250: Hash Accelerator 1 TX 11351: memcpy TX (to be used by the DMA driver for memcpy operations) 11452: SLIMbus or HSI channel 4 11553: SLIMbus or HSI channel 5 11654: SLIMbus or HSI channel 6 11755: SLIMbus or HSI channel 7 11856: memcpy (to be used by the DMA driver for memcpy operations) 11957: memcpy (to be used by the DMA driver for memcpy operations) 12058: memcpy (to be used by the DMA driver for memcpy operations) 12159: memcpy (to be used by the DMA driver for memcpy operations) 12260: memcpy (to be used by the DMA driver for memcpy operations) 12361: Crypto Accelerator 0 12462: Crypto Accelerator 0 TX or Hash Accelerator 0 TX 12563: Hash Accelerator 0 TX 126 127Example: 128 129 uart@80120000 { 130 compatible = "arm,pl011", "arm,primecell"; 131 reg = <0x80120000 0x1000>; 132 interrupts = <0 11 0x4>; 133 134 dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */ 135 <&dma 13 0 0x0>; /* Logical - MemToDev */ 136 dma-names = "rx", "rx"; 137 138 }; 139