1* STMicroelectronics Flexible Direct Memory Access Device Tree bindings 2 3The FDMA is a general-purpose direct memory access controller capable of 4supporting 16 independent DMA channels. It accepts up to 32 DMA requests. 5The FDMA is based on a Slim processor which requires a firmware. 6 7* FDMA Controller 8 9Required properties: 10- compatible : Should be one of 11 - st,stih407-fdma-mpe31-11, "st,slim-rproc"; 12 - st,stih407-fdma-mpe31-12, "st,slim-rproc"; 13 - st,stih407-fdma-mpe31-13, "st,slim-rproc"; 14- reg : Should contain an entry for each name in reg-names 15- reg-names : Must contain "slimcore", "dmem", "peripherals", "imem" entries 16- interrupts : Should contain one interrupt shared by all channels 17- dma-channels : Number of channels supported by the controller 18- #dma-cells : Must be <3>. See DMA client section below 19- clocks : Must contain an entry for each clock 20See: Documentation/devicetree/bindings/clock/clock-bindings.txt 21 22 23Example: 24 25 fdma0: dma-controller@8e20000 { 26 compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc"; 27 reg = <0x8e20000 0x8000>, 28 <0x8e30000 0x3000>, 29 <0x8e37000 0x1000>, 30 <0x8e38000 0x8000>; 31 reg-names = "slimcore", "dmem", "peripherals", "imem"; 32 clocks = <&clk_s_c0_flexgen CLK_FDMA>, 33 <&clk_s_c0_flexgen CLK_EXT2F_A9>, 34 <&clk_s_c0_flexgen CLK_EXT2F_A9>, 35 <&clk_s_c0_flexgen CLK_EXT2F_A9>; 36 interrupts = <GIC_SPI 5 IRQ_TYPE_NONE>; 37 dma-channels = <16>; 38 #dma-cells = <3>; 39 }; 40 41* DMA client 42 43Required properties: 44- dmas: Comma separated list of dma channel requests 45- dma-names: Names of the aforementioned requested channels 46 47Each dmas request consists of 4 cells: 481. A phandle pointing to the FDMA controller 492. The request line number 503. A 32bit mask specifying (see include/linux/platform_data/dma-st-fdma.h) 51 -bit 2-0: Holdoff value, dreq will be masked for 52 0x0: 0-0.5us 53 0x1: 0.5-1us 54 0x2: 1-1.5us 55 -bit 17: data swap 56 0x0: disabled 57 0x1: enabled 58 -bit 21: Increment Address 59 0x0: no address increment between transfers 60 0x1: increment address between transfers 61 -bit 22: 2 STBus Initiator Coprocessor interface 62 0x0: high priority port 63 0x1: low priority port 644. transfers type 65 0 free running 66 1 paced 67 68Example: 69 70 sti_uni_player2: sti-uni-player@2 { 71 compatible = "st,sti-uni-player"; 72 #sound-dai-cells = <0>; 73 st,syscfg = <&syscfg_core>; 74 clocks = <&clk_s_d0_flexgen CLK_PCM_2>; 75 assigned-clocks = <&clk_s_d0_flexgen CLK_PCM_2>; 76 assigned-clock-parents = <&clk_s_d0_quadfs 2>; 77 assigned-clock-rates = <50000000>; 78 reg = <0x8D82000 0x158>; 79 interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>; 80 dmas = <&fdma0 4 0 1>; 81 dai-name = "Uni Player #1 (DAC)"; 82 dma-names = "tx"; 83 st,uniperiph-id = <2>; 84 st,version = <5>; 85 st,mode = "PCM"; 86 }; 87