xref: /freebsd/sys/contrib/device-tree/Bindings/dma/st,stm32-dma.yaml (revision d485c77f203fb0f4cdc08dea5ff81631b51d8809) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/dma/st,stm32-dma.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: STMicroelectronics STM32 DMA Controller bindings
8
9description: |
10  The STM32 DMA is a general-purpose direct memory access controller capable of
11  supporting 8 independent DMA channels. Each channel can have up to 8 requests.
12  DMA clients connected to the STM32 DMA controller must use the format
13  described in the dma.txt file, using a four-cell specifier for each
14  channel: a phandle to the DMA controller plus the following four integer cells:
15    1. The channel id
16    2. The request line number
17    3. A 32bit mask specifying the DMA channel configuration which are device
18      dependent:
19        -bit 9: Peripheral Increment Address
20          0x0: no address increment between transfers
21          0x1: increment address between transfers
22        -bit 10: Memory Increment Address
23          0x0: no address increment between transfers
24          0x1: increment address between transfers
25        -bit 15: Peripheral Increment Offset Size
26          0x0: offset size is linked to the peripheral bus width
27          0x1: offset size is fixed to 4 (32-bit alignment)
28        -bit 16-17: Priority level
29          0x0: low
30          0x1: medium
31          0x2: high
32          0x3: very high
33    4. A 32bit bitfield value specifying DMA features which are device dependent:
34       -bit 0-1: DMA FIFO threshold selection
35         0x0: 1/4 full FIFO
36         0x1: 1/2 full FIFO
37         0x2: 3/4 full FIFO
38         0x3: full FIFO
39       -bit 2: DMA direct mode
40         0x0: FIFO mode with threshold selectable with bit 0-1
41         0x1: Direct mode: each DMA request immediately initiates a transfer
42              from/to the memory, FIFO is bypassed.
43
44
45maintainers:
46  - Amelie Delaunay <amelie.delaunay@st.com>
47
48allOf:
49  - $ref: "dma-controller.yaml#"
50
51properties:
52  "#dma-cells":
53    const: 4
54
55  compatible:
56    const: st,stm32-dma
57
58  reg:
59    maxItems: 1
60
61  clocks:
62    maxItems: 1
63
64  interrupts:
65    maxItems: 8
66    description: Should contain all of the per-channel DMA
67      interrupts in ascending order with respect to the
68      DMA channel index.
69
70  resets:
71    maxItems: 1
72
73  st,mem2mem:
74    $ref: /schemas/types.yaml#/definitions/flag
75    description: if defined, it indicates that the controller
76      supports memory-to-memory transfer
77
78required:
79  - compatible
80  - reg
81  - clocks
82  - interrupts
83
84examples:
85  - |
86    #include <dt-bindings/interrupt-controller/arm-gic.h>
87    #include <dt-bindings/clock/stm32mp1-clks.h>
88    #include <dt-bindings/reset/stm32mp1-resets.h>
89    dma-controller@40026400 {
90      compatible = "st,stm32-dma";
91      reg = <0x40026400 0x400>;
92      interrupts = <56>,
93                   <57>,
94                   <58>,
95                   <59>,
96                   <60>,
97                   <68>,
98                   <69>,
99                   <70>;
100      clocks = <&clk_hclk>;
101      #dma-cells = <4>;
102      st,mem2mem;
103      resets = <&rcc 150>;
104      dma-requests = <8>;
105    };
106
107...
108