1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/dma/socionext,uniphier-mio-dmac.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: UniPhier Media IO DMA controller 8 9description: | 10 This works as an external DMA engine for SD/eMMC controllers etc. 11 found in UniPhier LD4, Pro4, sLD8 SoCs. 12 13maintainers: 14 - Masahiro Yamada <yamada.masahiro@socionext.com> 15 16allOf: 17 - $ref: dma-controller.yaml# 18 19properties: 20 compatible: 21 const: socionext,uniphier-mio-dmac 22 23 reg: 24 maxItems: 1 25 26 interrupts: 27 description: | 28 A list of interrupt specifiers associated with the DMA channels. 29 The number of interrupt lines is SoC-dependent. 30 31 clocks: 32 maxItems: 1 33 34 resets: 35 maxItems: 1 36 37 '#dma-cells': 38 description: The single cell represents the channel index. 39 const: 1 40 41required: 42 - compatible 43 - reg 44 - interrupts 45 - clocks 46 - '#dma-cells' 47 48additionalProperties: false 49 50examples: 51 - | 52 // In the example below, "interrupts = <0 68 4>, <0 68 4>, ..." is not a 53 // typo. The first two channels share a single interrupt line. 54 55 dmac: dma-controller@5a000000 { 56 compatible = "socionext,uniphier-mio-dmac"; 57 reg = <0x5a000000 0x1000>; 58 interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>, 59 <0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>; 60 clocks = <&mio_clk 7>; 61 resets = <&mio_rst 7>; 62 #dma-cells = <1>; 63 }; 64