xref: /freebsd/sys/contrib/device-tree/Bindings/dma/snps,dma-spear1340.yaml (revision d485c77f203fb0f4cdc08dea5ff81631b51d8809) 
1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/dma/snps,dma-spear1340.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Synopsys Designware DMA Controller
8
9maintainers:
10  - Viresh Kumar <vireshk@kernel.org>
11  - Andy Shevchenko <andriy.shevchenko@linux.intel.com>
12
13allOf:
14  - $ref: "dma-controller.yaml#"
15
16properties:
17  compatible:
18    const: snps,dma-spear1340
19
20  "#dma-cells":
21    const: 3
22    description: |
23      First cell is a phandle pointing to the DMA controller. Second one is
24      the DMA request line number. Third cell is the memory master identifier
25      for transfers on dynamically allocated channel. Fourth cell is the
26      peripheral master identifier for transfers on an allocated channel.
27
28  reg:
29    maxItems: 1
30
31  interrupts:
32    maxItems: 1
33
34  clocks:
35    maxItems: 1
36
37  clock-names:
38    description: AHB interface reference clock.
39    const: hclk
40
41  dma-channels:
42    description: |
43      Number of DMA channels supported by the controller. In case if
44      not specified the driver will try to auto-detect this and
45      the rest of the optional parameters.
46    minimum: 1
47    maximum: 8
48
49  dma-requests:
50    minimum: 1
51    maximum: 16
52
53  dma-masters:
54    $ref: /schemas/types.yaml#definitions/uint32
55    description: |
56      Number of DMA masters supported by the controller. In case if
57      not specified the driver will try to auto-detect this and
58      the rest of the optional parameters.
59    minimum: 1
60    maximum: 4
61
62  chan_allocation_order:
63    $ref: /schemas/types.yaml#definitions/uint32
64    description: |
65      DMA channels allocation order specifier. Zero means ascending order
66      (first free allocated), while one - descending (last free allocated).
67    default: 0
68    enum: [0, 1]
69
70  chan_priority:
71    $ref: /schemas/types.yaml#definitions/uint32
72    description: |
73      DMA channels priority order. Zero means ascending channels priority
74      so the very first channel has the highest priority. While 1 means
75      descending priority (the last channel has the highest priority).
76    default: 0
77    enum: [0, 1]
78
79  block_size:
80    $ref: /schemas/types.yaml#definitions/uint32
81    description: Maximum block size supported by the DMA controller.
82    enum: [3, 7, 15, 31, 63, 127, 255, 511, 1023, 2047, 4095]
83
84  data-width:
85    $ref: /schemas/types.yaml#/definitions/uint32-array
86    description: Data bus width per each DMA master in bytes.
87    items:
88      maxItems: 4
89      items:
90        enum: [4, 8, 16, 32]
91
92  data_width:
93    $ref: /schemas/types.yaml#/definitions/uint32-array
94    deprecated: true
95    description: |
96      Data bus width per each DMA master in (2^n * 8) bits. This property is
97      deprecated. It' usage is discouraged in favor of data-width one. Moreover
98      the property incorrectly permits to define data-bus width of 8 and 16
99      bits, which is impossible in accordance with DW DMAC IP-core data book.
100    items:
101      maxItems: 4
102      items:
103        enum:
104          - 0 # 8 bits
105          - 1 # 16 bits
106          - 2 # 32 bits
107          - 3 # 64 bits
108          - 4 # 128 bits
109          - 5 # 256 bits
110        default: 0
111
112  multi-block:
113    $ref: /schemas/types.yaml#/definitions/uint32-array
114    description: |
115      LLP-based multi-block transfer supported by hardware per
116      each DMA channel.
117    items:
118      maxItems: 8
119      items:
120        enum: [0, 1]
121        default: 1
122
123  snps,max-burst-len:
124    $ref: /schemas/types.yaml#/definitions/uint32-array
125    description: |
126      Maximum length of the burst transactions supported by the controller.
127      This property defines the upper limit of the run-time burst setting
128      (CTLx.SRC_MSIZE/CTLx.DST_MSIZE fields) so the allowed burst length
129      will be from 1 to max-burst-len words. It's an array property with one
130      cell per channel in the units determined by the value set in the
131      CTLx.SRC_TR_WIDTH/CTLx.DST_TR_WIDTH fields (data width).
132    items:
133      maxItems: 8
134      items:
135        enum: [4, 8, 16, 32, 64, 128, 256]
136        default: 256
137
138  snps,dma-protection-control:
139    $ref: /schemas/types.yaml#definitions/uint32
140    description: |
141      Bits one-to-one passed to the AHB HPROT[3:1] bus. Each bit setting
142      indicates the following features: bit 0 - privileged mode,
143      bit 1 - DMA is bufferable, bit 2 - DMA is cacheable.
144    default: 0
145    minimum: 0
146    maximum: 7
147
148unevaluatedProperties: false
149
150required:
151  - compatible
152  - "#dma-cells"
153  - reg
154  - interrupts
155
156examples:
157  - |
158    dma-controller@fc000000 {
159      compatible = "snps,dma-spear1340";
160      reg = <0xfc000000 0x1000>;
161      interrupt-parent = <&vic1>;
162      interrupts = <12>;
163
164      dma-channels = <8>;
165      dma-requests = <16>;
166      dma-masters = <4>;
167      #dma-cells = <3>;
168
169      chan_allocation_order = <1>;
170      chan_priority = <1>;
171      block_size = <0xfff>;
172      data-width = <8 8>;
173      multi-block = <0 0 0 0 0 0 0 0>;
174      snps,max-burst-len = <16 16 4 4 4 4 4 4>;
175    };
176...
177