xref: /freebsd/sys/contrib/device-tree/Bindings/dma/renesas,rz-dmac.yaml (revision cb7aa33ac6cd46a5434798e50363136e64f3ae98) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas RZ/{G2L,G2UL,V2L} DMA Controller
8
9maintainers:
10  - Biju Das <biju.das.jz@bp.renesas.com>
11
12allOf:
13  - $ref: dma-controller.yaml#
14
15properties:
16  compatible:
17    items:
18      - enum:
19          - renesas,r9a07g043-dmac # RZ/G2UL
20          - renesas,r9a07g044-dmac # RZ/G2{L,LC}
21          - renesas,r9a07g054-dmac # RZ/V2L
22      - const: renesas,rz-dmac
23
24  reg:
25    items:
26      - description: Control and channel register block
27      - description: DMA extended resource selector block
28
29  interrupts:
30    maxItems: 17
31
32  interrupt-names:
33    items:
34      - const: error
35      - const: ch0
36      - const: ch1
37      - const: ch2
38      - const: ch3
39      - const: ch4
40      - const: ch5
41      - const: ch6
42      - const: ch7
43      - const: ch8
44      - const: ch9
45      - const: ch10
46      - const: ch11
47      - const: ch12
48      - const: ch13
49      - const: ch14
50      - const: ch15
51
52  clocks:
53    items:
54      - description: DMA main clock
55      - description: DMA register access clock
56
57  '#dma-cells':
58    const: 1
59    description:
60      The cell specifies the encoded MID/RID values of the DMAC port
61      connected to the DMA client and the slave channel configuration
62      parameters.
63      bits[0:9] - Specifies MID/RID value
64      bit[10] - Specifies DMA request high enable (HIEN)
65      bit[11] - Specifies DMA request detection type (LVL)
66      bits[12:14] - Specifies DMAACK output mode (AM)
67      bit[15] - Specifies Transfer Mode (TM)
68
69  dma-channels:
70    const: 16
71
72  power-domains:
73    maxItems: 1
74
75  resets:
76    items:
77      - description: Reset for DMA ARESETN reset terminal
78      - description: Reset for DMA RST_ASYNC reset terminal
79
80required:
81  - compatible
82  - reg
83  - interrupts
84  - interrupt-names
85  - clocks
86  - '#dma-cells'
87  - dma-channels
88  - power-domains
89  - resets
90
91additionalProperties: false
92
93examples:
94  - |
95    #include <dt-bindings/interrupt-controller/arm-gic.h>
96    #include <dt-bindings/clock/r9a07g044-cpg.h>
97
98    dmac: dma-controller@11820000 {
99        compatible = "renesas,r9a07g044-dmac",
100                     "renesas,rz-dmac";
101        reg = <0x11820000 0x10000>,
102              <0x11830000 0x10000>;
103        interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
104                     <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
105                     <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
106                     <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
107                     <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
108                     <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
109                     <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
110                     <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
111                     <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
112                     <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
113                     <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
114                     <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
115                     <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
116                     <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
117                     <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
118                     <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
119                     <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
120        interrupt-names = "error",
121                          "ch0", "ch1", "ch2", "ch3",
122                          "ch4", "ch5", "ch6", "ch7",
123                          "ch8", "ch9", "ch10", "ch11",
124                          "ch12", "ch13", "ch14", "ch15";
125        clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
126                 <&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
127        power-domains = <&cpg>;
128        resets = <&cpg R9A07G044_DMAC_ARESETN>,
129                 <&cpg R9A07G044_DMAC_RST_ASYNC>;
130        #dma-cells = <1>;
131        dma-channels = <16>;
132    };
133