xref: /freebsd/sys/contrib/device-tree/Bindings/dma/renesas,rz-dmac.yaml (revision 9286d46a794f25482880d29864a8901ef6666fae) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas RZ/{G2L,G2UL,V2L} DMA Controller
8
9maintainers:
10  - Biju Das <biju.das.jz@bp.renesas.com>
11
12allOf:
13  - $ref: dma-controller.yaml#
14
15properties:
16  compatible:
17    items:
18      - enum:
19          - renesas,r9a07g043-dmac # RZ/G2UL
20          - renesas,r9a07g044-dmac # RZ/G2{L,LC}
21          - renesas,r9a07g054-dmac # RZ/V2L
22      - const: renesas,rz-dmac
23
24  reg:
25    items:
26      - description: Control and channel register block
27      - description: DMA extended resource selector block
28
29  interrupts:
30    maxItems: 17
31
32  interrupt-names:
33    items:
34      - const: error
35      - const: ch0
36      - const: ch1
37      - const: ch2
38      - const: ch3
39      - const: ch4
40      - const: ch5
41      - const: ch6
42      - const: ch7
43      - const: ch8
44      - const: ch9
45      - const: ch10
46      - const: ch11
47      - const: ch12
48      - const: ch13
49      - const: ch14
50      - const: ch15
51
52  clocks:
53    items:
54      - description: DMA main clock
55      - description: DMA register access clock
56
57  clock-names:
58    items:
59      - const: main
60      - const: register
61
62  '#dma-cells':
63    const: 1
64    description:
65      The cell specifies the encoded MID/RID values of the DMAC port
66      connected to the DMA client and the slave channel configuration
67      parameters.
68      bits[0:9] - Specifies MID/RID value
69      bit[10] - Specifies DMA request high enable (HIEN)
70      bit[11] - Specifies DMA request detection type (LVL)
71      bits[12:14] - Specifies DMAACK output mode (AM)
72      bit[15] - Specifies Transfer Mode (TM)
73
74  dma-channels:
75    const: 16
76
77  power-domains:
78    maxItems: 1
79
80  resets:
81    items:
82      - description: Reset for DMA ARESETN reset terminal
83      - description: Reset for DMA RST_ASYNC reset terminal
84
85  reset-names:
86    items:
87      - const: arst
88      - const: rst_async
89
90required:
91  - compatible
92  - reg
93  - interrupts
94  - interrupt-names
95  - clocks
96  - clock-names
97  - '#dma-cells'
98  - dma-channels
99  - power-domains
100  - resets
101  - reset-names
102
103additionalProperties: false
104
105examples:
106  - |
107    #include <dt-bindings/interrupt-controller/arm-gic.h>
108    #include <dt-bindings/clock/r9a07g044-cpg.h>
109
110    dmac: dma-controller@11820000 {
111        compatible = "renesas,r9a07g044-dmac",
112                     "renesas,rz-dmac";
113        reg = <0x11820000 0x10000>,
114              <0x11830000 0x10000>;
115        interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
116                     <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
117                     <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
118                     <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
119                     <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
120                     <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
121                     <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
122                     <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
123                     <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
124                     <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
125                     <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
126                     <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
127                     <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
128                     <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
129                     <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
130                     <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
131                     <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
132        interrupt-names = "error",
133                          "ch0", "ch1", "ch2", "ch3",
134                          "ch4", "ch5", "ch6", "ch7",
135                          "ch8", "ch9", "ch10", "ch11",
136                          "ch12", "ch13", "ch14", "ch15";
137        clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
138                 <&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
139        clock-names = "main", "register";
140        power-domains = <&cpg>;
141        resets = <&cpg R9A07G044_DMAC_ARESETN>,
142                 <&cpg R9A07G044_DMAC_RST_ASYNC>;
143        reset-names = "arst", "rst_async";
144        #dma-cells = <1>;
145        dma-channels = <16>;
146    };
147