1* NVIDIA Tegra APB DMA controller 2 3Required properties: 4- compatible: Should be "nvidia,<chip>-apbdma" 5- reg: Should contain DMA registers location and length. This should include 6 all of the per-channel registers. 7- interrupts: Should contain all of the per-channel DMA interrupts. 8- clocks: Must contain one entry, for the module clock. 9 See ../clocks/clock-bindings.txt for details. 10- resets : Must contain an entry for each entry in reset-names. 11 See ../reset/reset.txt for details. 12- reset-names : Must include the following entries: 13 - dma 14- #dma-cells : Must be <1>. This dictates the length of DMA specifiers in 15 client nodes' dmas properties. The specifier represents the DMA request 16 select value for the peripheral. For more details, consult the Tegra TRM's 17 documentation of the APB DMA channel control register REQ_SEL field. 18 19Examples: 20 21apbdma: dma@6000a000 { 22 compatible = "nvidia,tegra20-apbdma"; 23 reg = <0x6000a000 0x1200>; 24 interrupts = < 0 136 0x04 25 0 137 0x04 26 0 138 0x04 27 0 139 0x04 28 0 140 0x04 29 0 141 0x04 30 0 142 0x04 31 0 143 0x04 32 0 144 0x04 33 0 145 0x04 34 0 146 0x04 35 0 147 0x04 36 0 148 0x04 37 0 149 0x04 38 0 150 0x04 39 0 151 0x04 >; 40 clocks = <&tegra_car 34>; 41 resets = <&tegra_car 34>; 42 reset-names = "dma"; 43 #dma-cells = <1>; 44}; 45