xref: /freebsd/sys/contrib/device-tree/Bindings/dma/mediatek,uart-dma.yaml (revision 3a3af6b2a160bea72509a9d5ef84e25906b0478a) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/dma/mediatek,uart-dma.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek UART APDMA controller
8
9maintainers:
10  - Long Cheng <long.cheng@mediatek.com>
11
12description: |
13  The MediaTek UART APDMA controller provides DMA capabilities
14  for the UART peripheral bus.
15
16allOf:
17  - $ref: "dma-controller.yaml#"
18
19properties:
20  compatible:
21    oneOf:
22      - items:
23          - enum:
24              - mediatek,mt2712-uart-dma
25              - mediatek,mt8516-uart-dma
26          - const: mediatek,mt6577-uart-dma
27      - enum:
28          - mediatek,mt6577-uart-dma
29
30  reg:
31    minItems: 1
32    maxItems: 16
33
34  interrupts:
35    description: |
36      TX, RX interrupt lines for each UART APDMA channel
37    minItems: 1
38    maxItems: 16
39
40  clocks:
41    description: Must contain one entry for the APDMA main clock
42    maxItems: 1
43
44  clock-names:
45    const: apdma
46
47  "#dma-cells":
48    const: 1
49    description: |
50      The first cell specifies the UART APDMA channel number
51
52  dma-requests:
53    description: |
54      Number of virtual channels of the UART APDMA controller
55    maximum: 16
56
57  mediatek,dma-33bits:
58    type: boolean
59    description: Enable 33-bits UART APDMA support
60
61required:
62  - compatible
63  - reg
64  - interrupts
65
66additionalProperties: false
67
68if:
69  not:
70    required:
71      - dma-requests
72then:
73  properties:
74    interrupts:
75      maxItems: 8
76    reg:
77      maxItems: 8
78
79examples:
80  - |
81    #include <dt-bindings/interrupt-controller/arm-gic.h>
82    #include <dt-bindings/clock/mt2712-clk.h>
83    soc {
84        #address-cells = <2>;
85        #size-cells = <2>;
86
87        apdma: dma-controller@11000400 {
88            compatible = "mediatek,mt2712-uart-dma",
89                         "mediatek,mt6577-uart-dma";
90            reg = <0 0x11000400 0 0x80>,
91                  <0 0x11000480 0 0x80>,
92                  <0 0x11000500 0 0x80>,
93                  <0 0x11000580 0 0x80>,
94                  <0 0x11000600 0 0x80>,
95                  <0 0x11000680 0 0x80>,
96                  <0 0x11000700 0 0x80>,
97                  <0 0x11000780 0 0x80>,
98                  <0 0x11000800 0 0x80>,
99                  <0 0x11000880 0 0x80>,
100                  <0 0x11000900 0 0x80>,
101                  <0 0x11000980 0 0x80>;
102            interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,
103                         <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
104                         <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,
105                         <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,
106                         <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,
107                         <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,
108                         <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,
109                         <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>,
110                         <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>,
111                         <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>,
112                         <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>,
113                         <GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>;
114            dma-requests = <12>;
115            clocks = <&pericfg CLK_PERI_AP_DMA>;
116            clock-names = "apdma";
117            mediatek,dma-33bits;
118            #dma-cells = <1>;
119        };
120    };
121
122...
123