xref: /freebsd/sys/contrib/device-tree/Bindings/dma/ingenic,dma.yaml (revision aa1a8ff2d6dbc51ef058f46f3db5a8bb77967145)
1c66ec88fSEmmanuel Vadot# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2c66ec88fSEmmanuel Vadot%YAML 1.2
3c66ec88fSEmmanuel Vadot---
4c66ec88fSEmmanuel Vadot$id: http://devicetree.org/schemas/dma/ingenic,dma.yaml#
5c66ec88fSEmmanuel Vadot$schema: http://devicetree.org/meta-schemas/core.yaml#
6c66ec88fSEmmanuel Vadot
78bab661aSEmmanuel Vadottitle: Ingenic SoCs DMA Controller
8c66ec88fSEmmanuel Vadot
9c66ec88fSEmmanuel Vadotmaintainers:
10c66ec88fSEmmanuel Vadot  - Paul Cercueil <paul@crapouillou.net>
11c66ec88fSEmmanuel Vadot
12c66ec88fSEmmanuel VadotallOf:
13cb7aa33aSEmmanuel Vadot  - $ref: dma-controller.yaml#
14c66ec88fSEmmanuel Vadot
15c66ec88fSEmmanuel Vadotproperties:
16c66ec88fSEmmanuel Vadot  compatible:
17e67e8565SEmmanuel Vadot    oneOf:
18e67e8565SEmmanuel Vadot      - enum:
19c66ec88fSEmmanuel Vadot          - ingenic,jz4740-dma
20c66ec88fSEmmanuel Vadot          - ingenic,jz4725b-dma
218bab661aSEmmanuel Vadot          - ingenic,jz4755-dma
225def4c47SEmmanuel Vadot          - ingenic,jz4760-dma
23e67e8565SEmmanuel Vadot          - ingenic,jz4760-bdma
24e67e8565SEmmanuel Vadot          - ingenic,jz4760-mdma
255def4c47SEmmanuel Vadot          - ingenic,jz4760b-dma
26e67e8565SEmmanuel Vadot          - ingenic,jz4760b-bdma
27e67e8565SEmmanuel Vadot          - ingenic,jz4760b-mdma
28c66ec88fSEmmanuel Vadot          - ingenic,jz4770-dma
29c66ec88fSEmmanuel Vadot          - ingenic,jz4780-dma
30c66ec88fSEmmanuel Vadot          - ingenic,x1000-dma
31c66ec88fSEmmanuel Vadot          - ingenic,x1830-dma
32e67e8565SEmmanuel Vadot      - items:
33e67e8565SEmmanuel Vadot          - const: ingenic,jz4770-bdma
34e67e8565SEmmanuel Vadot          - const: ingenic,jz4760b-bdma
35c66ec88fSEmmanuel Vadot
36c66ec88fSEmmanuel Vadot  reg:
37c66ec88fSEmmanuel Vadot    items:
38c66ec88fSEmmanuel Vadot      - description: Channel-specific registers
39c66ec88fSEmmanuel Vadot      - description: System control registers
40c66ec88fSEmmanuel Vadot
41c66ec88fSEmmanuel Vadot  interrupts:
42c66ec88fSEmmanuel Vadot    maxItems: 1
43c66ec88fSEmmanuel Vadot
44c66ec88fSEmmanuel Vadot  clocks:
45c66ec88fSEmmanuel Vadot    maxItems: 1
46c66ec88fSEmmanuel Vadot
47c66ec88fSEmmanuel Vadot  "#dma-cells":
48e67e8565SEmmanuel Vadot    enum: [2, 3]
49c66ec88fSEmmanuel Vadot    description: >
50c66ec88fSEmmanuel Vadot      DMA clients must use the format described in dma.txt, giving a phandle
51e67e8565SEmmanuel Vadot      to the DMA controller plus the following integer cells:
52c66ec88fSEmmanuel Vadot
53e67e8565SEmmanuel Vadot      - Request type: The DMA request type specifies the device endpoint that
54e67e8565SEmmanuel Vadot        will be the source or destination of the DMA transfer.
55e67e8565SEmmanuel Vadot        If "#dma-cells" is 2, the request type is a single cell, and the
56e67e8565SEmmanuel Vadot        direction will be unidirectional (either RX or TX but not both).
57e67e8565SEmmanuel Vadot        If "#dma-cells" is 3, the request type has two cells; the first
58e67e8565SEmmanuel Vadot        one corresponds to the host to device direction (TX), the second one
59e67e8565SEmmanuel Vadot        corresponds to the device to host direction (RX). The DMA channel is
60e67e8565SEmmanuel Vadot        then bidirectional.
61c66ec88fSEmmanuel Vadot
62c66ec88fSEmmanuel Vadot      - Channel: If set to 0xffffffff, any available channel will be allocated
63c66ec88fSEmmanuel Vadot        for the client. Otherwise, the exact channel specified will be used.
64c66ec88fSEmmanuel Vadot        The channel should be reserved on the DMA controller using the
65c66ec88fSEmmanuel Vadot        ingenic,reserved-channels property.
66c66ec88fSEmmanuel Vadot
67c66ec88fSEmmanuel Vadot  ingenic,reserved-channels:
685def4c47SEmmanuel Vadot    $ref: /schemas/types.yaml#/definitions/uint32
69c66ec88fSEmmanuel Vadot    description: >
70c66ec88fSEmmanuel Vadot      Bitmask of channels to reserve for devices that need a specific
71*aa1a8ff2SEmmanuel Vadot      channel. These channels will only be assigned when explicitly
72c66ec88fSEmmanuel Vadot      requested by a client. The primary use for this is channels 0 and
73c66ec88fSEmmanuel Vadot      1, which can be configured to have special behaviour for NAND/BCH
74c66ec88fSEmmanuel Vadot      when using programmable firmware.
75c66ec88fSEmmanuel Vadot
76c66ec88fSEmmanuel Vadotrequired:
77c66ec88fSEmmanuel Vadot  - compatible
78c66ec88fSEmmanuel Vadot  - reg
79c66ec88fSEmmanuel Vadot  - interrupts
80c66ec88fSEmmanuel Vadot  - clocks
81c66ec88fSEmmanuel Vadot
826be33864SEmmanuel VadotunevaluatedProperties: false
836be33864SEmmanuel Vadot
84c66ec88fSEmmanuel Vadotexamples:
85c66ec88fSEmmanuel Vadot  - |
868cc087a1SEmmanuel Vadot    #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
87c66ec88fSEmmanuel Vadot    dma: dma-controller@13420000 {
88c66ec88fSEmmanuel Vadot      compatible = "ingenic,jz4780-dma";
89c66ec88fSEmmanuel Vadot      reg = <0x13420000 0x400>, <0x13421000 0x40>;
90c66ec88fSEmmanuel Vadot
91c66ec88fSEmmanuel Vadot      interrupt-parent = <&intc>;
92c66ec88fSEmmanuel Vadot      interrupts = <10>;
93c66ec88fSEmmanuel Vadot
94c66ec88fSEmmanuel Vadot      clocks = <&cgu JZ4780_CLK_PDMA>;
95c66ec88fSEmmanuel Vadot
96c66ec88fSEmmanuel Vadot      #dma-cells = <2>;
97c66ec88fSEmmanuel Vadot
98c66ec88fSEmmanuel Vadot      ingenic,reserved-channels = <0x3>;
99c66ec88fSEmmanuel Vadot    };
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