1* Freescale Smart Direct Memory Access (SDMA) Controller for i.MX 2 3Required properties: 4- compatible : Should be one of 5 "fsl,imx25-sdma" 6 "fsl,imx31-sdma", "fsl,imx31-to1-sdma", "fsl,imx31-to2-sdma" 7 "fsl,imx35-sdma", "fsl,imx35-to1-sdma", "fsl,imx35-to2-sdma" 8 "fsl,imx51-sdma" 9 "fsl,imx53-sdma" 10 "fsl,imx6q-sdma" 11 "fsl,imx7d-sdma" 12 "fsl,imx8mq-sdma" 13 "fsl,imx8mm-sdma" 14 "fsl,imx8mn-sdma" 15 "fsl,imx8mp-sdma" 16 The -to variants should be preferred since they allow to determine the 17 correct ROM script addresses needed for the driver to work without additional 18 firmware. 19- reg : Should contain SDMA registers location and length 20- interrupts : Should contain SDMA interrupt 21- #dma-cells : Must be <3>. 22 The first cell specifies the DMA request/event ID. See details below 23 about the second and third cell. 24- fsl,sdma-ram-script-name : Should contain the full path of SDMA RAM 25 scripts firmware 26 27The second cell of dma phandle specifies the peripheral type of DMA transfer. 28The full ID of peripheral types can be found below. 29 30 ID transfer type 31 --------------------- 32 0 MCU domain SSI 33 1 Shared SSI 34 2 MMC 35 3 SDHC 36 4 MCU domain UART 37 5 Shared UART 38 6 FIRI 39 7 MCU domain CSPI 40 8 Shared CSPI 41 9 SIM 42 10 ATA 43 11 CCM 44 12 External peripheral 45 13 Memory Stick Host Controller 46 14 Shared Memory Stick Host Controller 47 15 DSP 48 16 Memory 49 17 FIFO type Memory 50 18 SPDIF 51 19 IPU Memory 52 20 ASRC 53 21 ESAI 54 22 SSI Dual FIFO (needs firmware ver >= 2) 55 23 Shared ASRC 56 24 SAI 57 58The third cell specifies the transfer priority as below. 59 60 ID transfer priority 61 ------------------------- 62 0 High 63 1 Medium 64 2 Low 65 66Optional properties: 67 68- gpr : The phandle to the General Purpose Register (GPR) node. 69- fsl,sdma-event-remap : Register bits of sdma event remap, the format is 70 <reg shift val>. 71 reg is the GPR register offset. 72 shift is the bit position inside the GPR register. 73 val is the value of the bit (0 or 1). 74 75Examples: 76 77sdma@83fb0000 { 78 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; 79 reg = <0x83fb0000 0x4000>; 80 interrupts = <6>; 81 #dma-cells = <3>; 82 fsl,sdma-ram-script-name = "sdma-imx51.bin"; 83}; 84 85DMA clients connected to the i.MX SDMA controller must use the format 86described in the dma.txt file. 87 88Examples: 89 90ssi2: ssi@70014000 { 91 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 92 reg = <0x70014000 0x4000>; 93 interrupts = <30>; 94 clocks = <&clks 49>; 95 dmas = <&sdma 24 1 0>, 96 <&sdma 25 1 0>; 97 dma-names = "rx", "tx"; 98 fsl,fifo-depth = <15>; 99}; 100 101Using the fsl,sdma-event-remap property: 102 103If we want to use SDMA on the SAI1 port on a MX6SX: 104 105&sdma { 106 gpr = <&gpr>; 107 /* SDMA events remap for SAI1_RX and SAI1_TX */ 108 fsl,sdma-event-remap = <0 15 1>, <0 16 1>; 109}; 110 111The fsl,sdma-event-remap property in this case has two values: 112- <0 15 1> means that the offset is 0, so GPR0 is the register of the 113SDMA remap. Bit 15 of GPR0 selects between UART4_RX and SAI1_RX. 114Setting bit 15 to 1 selects SAI1_RX. 115- <0 16 1> means that the offset is 0, so GPR0 is the register of the 116SDMA remap. Bit 16 of GPR0 selects between UART4_TX and SAI1_TX. 117Setting bit 16 to 1 selects SAI1_TX. 118